top_tbw.tfw

Verilog编程

// E:\FPGA_PROGRAM\ISE6.1\TST
// Verilog Test fixture created by
// HDL Bencher 6.1i
// Thu May 24 09:33:28 2007
// 
// Notes:
// 1) This test fixture has been automatically generated from
//   your Test Bench Waveform
// 2) To use this as a user modifiable test fixture do the following:
//   - Save it as a file with a .tf extension (i.e. File->Save As...)
//   - Add it to your project as a testbench source (i.e. Project->Add Source...)
// 

`timescale 1ns/1ns

`define F_ASSERT	2
`define s4	4
`define F_IDLE	1
`define FCWIDTH	2
`define C_ACTIVE	3
`define IF0	1
`define s1	1
`define IF1	2
`define TCKO	0
`define C_WRITE	4
`define F_DEASSERT	4
`define s2	2
`define C_NOP	7
`define C_P_CHRG	2
`define state_delay	6
`define C_REFRSH	1
`define s3	3
`define IF2	3
`define N	5
`define Q	25
`define RES	5
`define s0	0
`define FWIDTH	32
`define C_READ	5
`define D	10
`define BR0	0
`define FDEPTH	4
`define C_L_MODE	0
`define OD	4
`define C_NOP	7
`define IF2	3
`define D	10
`define C_READ	5
`define C_ACTIVE	3
`define F_IDLE	1
`define F_IDLE	1
`define F_ASSERT	2

module top_tbw;
	reg clkin;
	reg rst;
	reg NCS0_n;
	reg NWE_n;
	reg [4:0] addr;
	reg [15:0] DataIN;
	wire [7:0] SINE1;
	wire [7:0] SINE2;
	wire [7:0] SINE3;
	wire [7:0] SINE4;
	wire [7:0] SINE5;
	wire [7:0] SINE6;
	wire clk_out;

	defparam UUT.wordwidth_data = 16;
	defparam UUT.memsize_data = 32;

	top UUT (
		.clkin(clkin),
		.rst(rst),
		.NCS0_n(NCS0_n),
		.NWE_n(NWE_n),
		.addr(addr),
		.DataIN(DataIN),
		.SINE1(SINE1),
		.SINE2(SINE2),
		.SINE3(SINE3),
		.SINE4(SINE4),
		.SINE5(SINE5),
		.SINE6(SINE6),
		.clk_out(clk_out)
	);

	integer TX_FILE;
	integer TX_ERROR;

always
begin 			//clock process
	clkin = 1'b0;
	#2
	clkin = 1'b1;
	#2
	#8
	clkin = 1'b0;
	#8
	clkin = 1'b0;
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("results.txt");

	// --------------------
	rst = 1'b0;
	NCS0_n = 1'b1;
	NWE_n = 1'b1;
	addr = 5'b00000; //0
	DataIN = 16'b0000000000000000; //0
	// --------------------
	#20 // Time=20 ns
	rst = 1'b1;
	// --------------------

	if (TX_ERROR == 0) begin
		$display("No errors or warnings");
		$fdisplay(TX_FILE,"No errors or warnings");
	end else begin
		$display("%d errors found in simulation",TX_ERROR);
		$fdisplay(TX_FILE,"%d errors found in simulation",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task CHECK_SINE1;
	input [7:0] NEXT_SINE1;

	#0 begin
		if (NEXT_SINE1 !== SINE1) begin
			$display("Error at time=%dns SINE1=%b, expected=%b",
				$time, SINE1, NEXT_SINE1);
			$fdisplay(TX_FILE,"Error at time=%dns SINE1=%b, expected=%b",
				$time, SINE1, NEXT_SINE1);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_SINE2;
	input [7:0] NEXT_SINE2;

	#0 begin
		if (NEXT_SINE2 !== SINE2) begin
			$display("Error at time=%dns SINE2=%b, expected=%b",
				$time, SINE2, NEXT_SINE2);
			$fdisplay(TX_FILE,"Error at time=%dns SINE2=%b, expected=%b",
				$time, SINE2, NEXT_SINE2);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_SINE3;
	input [7:0] NEXT_SINE3;

	#0 begin
		if (NEXT_SINE3 !== SINE3) begin
			$display("Error at time=%dns SINE3=%b, expected=%b",
				$time, SINE3, NEXT_SINE3);
			$fdisplay(TX_FILE,"Error at time=%dns SINE3=%b, expected=%b",
				$time, SINE3, NEXT_SINE3);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_SINE4;
	input [7:0] NEXT_SINE4;

	#0 begin
		if (NEXT_SINE4 !== SINE4) begin
			$display("Error at time=%dns SINE4=%b, expected=%b",
				$time, SINE4, NEXT_SINE4);
			$fdisplay(TX_FILE,"Error at time=%dns SINE4=%b, expected=%b",
				$time, SINE4, NEXT_SINE4);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_SINE5;
	input [7:0] NEXT_SINE5;

	#0 begin
		if (NEXT_SINE5 !== SINE5) begin
			$display("Error at time=%dns SINE5=%b, expected=%b",
				$time, SINE5, NEXT_SINE5);
			$fdisplay(TX_FILE,"Error at time=%dns SINE5=%b, expected=%b",
				$time, SINE5, NEXT_SINE5);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_SINE6;
	input [7:0] NEXT_SINE6;

	#0 begin
		if (NEXT_SINE6 !== SINE6) begin
			$display("Error at time=%dns SINE6=%b, expected=%b",
				$time, SINE6, NEXT_SINE6);
			$fdisplay(TX_FILE,"Error at time=%dns SINE6=%b, expected=%b",
				$time, SINE6, NEXT_SINE6);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_clk_out;
	input NEXT_clk_out;

	#0 begin
		if (NEXT_clk_out !== clk_out) begin
			$display("Error at time=%dns clk_out=%b, expected=%b",
				$time, clk_out, NEXT_clk_out);
			$fdisplay(TX_FILE,"Error at time=%dns clk_out=%b, expected=%b",
				$time, clk_out, NEXT_clk_out);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

endmodule