代码搜索：FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/157209/11730241

txt 双向总线.txt

VHDL: Bidirectional Bus download from: http://www.fpga.com.cn bidir.vhd (Tri-state bus implementation) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY bidir IS PORT( bi
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www.eeworm.com/read/345690/11795147

txt 雙向總線(注2).txt

VHDL: Bidirectional Bus download from: http://www.fpga.com.cn bidir.vhd (Tri-state bus implementation) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY bidir IS PORT( bi
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www.eeworm.com/read/258170/11880744

txt pci_arbiter_readme.txt

fpga reference design Offer:QuickLogic PCI Arbiter: Files: \APPS\pci arbiter\pci_arb.exe PCI Master/Target Design: Files: \APPS\PCI\MASTER\*.* Top Level Design: TOP.SCH Simulation Test Fixtur
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www.eeworm.com/read/339660/12212195

vhd usbcomm.vhd

library IEEE; use IEEE.STD_LOGIC_1164.all; entity USBcomm is port( --FPGA信号 A: in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线 DIN: in STD_LOGIC_VECTOR(7 downto 0); -
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www.eeworm.com/read/338600/12292585

txt pci_arbiter_readme.txt

fpga reference design Offer:QuickLogic PCI Arbiter: Files: \APPS\pci arbiter\pci_arb.exe PCI Master/Target Design: Files: \APPS\PCI\MASTER\*.* Top Level Design: TOP.SCH Simulation Test Fixtur
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www.eeworm.com/read/129570/14237265

vhd alu1232.vhd

-- -- PROJECT: OpenUP - The uP1232a fpga-processor -- http://www.dte.eis.uva.es/OpenProjects/OpenUP/index.htm -- -- Santiago de Pablo -- Copyright (c) 2000. All Rights Reserved. -- -- GPL:
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www.eeworm.com/read/227189/14437612

txt 双向总线（注2）.txt

VHDL: Bidirectional Bus download from: http://www.fpga.com.cn bidir.vhd (Tri-state bus implementation) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY bidir IS PORT( bi
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www.eeworm.com/read/208531/15245747

txt 4位乘法器.txt

VHDL: Bidirectional Bus download from: http://www.fpga.com.cn bidir.vhd (Tri-state bus implementation) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY bidir IS PORT( bi
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www.eeworm.com/read/208531/15245755

txt 双向总线（.txt

VHDL: Bidirectional Bus download from: http://www.fpga.com.cn bidir.vhd (Tri-state bus implementation) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY bidir IS PORT( bi
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www.eeworm.com/read/17492/732734

qsf quartus_cone.qsf

set_global_assignment -name TOP_LEVEL_ENTITY fpga64_top # Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools
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