alu1232.vhd

VHDL开发的计数器。源程序不复杂

--
-- PROJECT:	OpenUP - The uP1232a fpga-processor
--		http://www.dte.eis.uva.es/OpenProjects/OpenUP/index.htm
--
--		Santiago de Pablo
--		Copyright (c) 2000. All Rights Reserved.
--
--		GPL: You may freely copy, change, and distribute it,
--		but you may not impose restrictions on further distribution,
--		and you must make the source code available.
--
-- AUTHOR:	Santiago de Pablo - [e-mail]
--		Department of Electronics Technology
--		University of Valladolid (Spain)
--
-- MODULE:	ALU1232.vhd	The ALU of the uP1232
--
-- DESCRIPTION:	An 8-bit ALU with 16 operations: logic, arithmetic, shifts.
--
-- REVISION:	0.14	28-NOV-2000	Fixed bug in Carry when SUB and SBC
--		0.12	10-OCT-2000	Ok
--		0.11	29-AGO-2000	Initial design
--
-- TO DO LIST:	Check VHDL style.
--
-- OPCODES:	LD   Rm,Sm	SHR  Rm,Sm	NOT Rm,Sm	ADD Rm,Sm
--		INC  Rm,Sm	DIV2 Rm,Sm	OR  Rm,Sm	SUB Rm,Sm
--		DEC  Rm,Sm	RR   Rm,Sm	AND Rm,Sm	ADC Rm,Sm
--		SETCF/CLRCF	RRC  Rm,Sm	XOR Rm,Sm	SBC Rm,Sm
--

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;

entity ALU1232 is
port(
	InA, InB	: in  std_logic_vector(7 downto 0);	-- Data Inputs.
	Op		: in  std_logic_vector(3 downto 0);	-- Operation Code.
	CarryIn		: in  std_logic;			-- Carry Input.
	AluOut		: out std_logic_vector(7 downto 0);	-- Output Value.
	CarryOut	: out std_logic				-- Carry Output.
);
end ALU1232;

architecture RTL of ALU1232 is

	signal	AluAv,  AluBv,  AluCv,  AluDv	: std_logic_vector(7 downto 0);
	signal	AluAci, AluAco, AluDci, AluDco	: std_logic_vector(7 downto 0);
	signal	AluMaskA, AluMaskD		: std_logic_vector(7 downto 0);
	signal	AluAc,  AluBc,  AluCc,  AluDc	: std_logic;

begin

	AluMaskA <= (others => Op(1));
	AluMaskD <= (others => Op(0));

	-- R = S; R = S + 1; R = S - 1 (S + 255); CFF = 1 (R = R + 256).
	AluAci <= AluAco(6 downto 0) & Op(0);
	AluAco <= (AluMaskA and InB) or (AluMaskA and AluAci) or (InB and AluAci);
	AluAv  <= AluMaskA xor InB xor AluAci;
	AluAc  <= AluAco(7);

	-- R = SHR S; R = S / 2; R = RR S; R = RRC S.
	AluBc <= InB(0);
	AluBv <= '0'    & InB(7 downto 1) when Op(1 downto 0) = "00"	else
		InB(7)  & InB(7 downto 1) when Op(1 downto 0) = "01"	else
		InB(0)  & InB(7 downto 1) when Op(1 downto 0) = "10"	else
		CarryIn & InB(7 downto 1);

	-- R = NOT S; R = R  OR S; R = R AND S; R = R XOR S.
	AluCc <=	'0';
	AluCv <=    not InB when Op(1 downto 0) = "00"	else
		InA  or InB when Op(1 downto 0) = "01"	else
		InA and InB when Op(1 downto 0) = "10"	else
		InA xor InB;

	-- R = R + S; R = R - S; R = R + S + CFF; R = R - S - CFF.
	AluDci <= AluDco(6 downto 0) & ((CarryIn and Op(1)) xor Op(0));
	AluDco <= (InA and (InB xor AluMaskD)) or (InA and AluDci) or ((InB xor AluMaskD) and AluDci);
	AluDv  <= InA xor (InB xor AluMaskD) xor AluDci;
	AluDc  <= AluDco(7) xor Op(0);

	-- Outputs
	AluOut <=
		AluAv	when Op(3 downto 2) = "00"	else
		AluBv	when Op(3 downto 2) = "01"	else
		AluCv	when Op(3 downto 2) = "10"	else
		AluDv;
	CarryOut <=
		AluAc	when Op(3 downto 2) = "00"	else
		AluBc	when Op(3 downto 2) = "01"	else
		AluCc	when Op(3 downto 2) = "10"	else
		AluDc;

end RTL;

-- End of File.