代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
代码结果 10,000
www.eeworm.com/read/319921/13439523
txt 双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
www.eeworm.com/read/316203/13528465
txt bidir.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
www.eeworm.com/read/315669/13538547
prj cmos_fifo_usb.prj
KEY LIBERO "8.0"
KEY CAPTURE "8.0.0.40"
KEY DEFAULT_IMPORT_LOC "F:\FPGA_TOP0415\hdl"
KEY DEFAULT_OPEN_LOC "C:\Documents and Settings\Administrator\桌面"
KEY HDLTechnology "VERILOG"
KEY VendorTechno
www.eeworm.com/read/312754/13605437
txt 双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
www.eeworm.com/read/305986/13755608
txt 双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
www.eeworm.com/read/302415/13836081
c lcd.c
/*********************************************************************
* 标题: 基于HD44780的1602简单驱动(C51)
* 文件: lcd.c
* 作者:
* 参考: AVR单片机与CPLD/FPGA综合应用入门
* 日期: 2007.5.10
* 修改: 2007.5.26
www.eeworm.com/read/382666/6286498
txt 双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
www.eeworm.com/read/494695/6360559
txt 双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
www.eeworm.com/read/487908/6501838
txt 双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
www.eeworm.com/read/478253/6722767
vhd usbcomm.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity USBcomm is
port(
--FPGA信号
A: in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
DIN: in STD_LOGIC_VECTOR(7 downto 0); -