代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
代码结果 10,000
www.eeworm.com/read/227189/14437608
vhd 简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
www.eeworm.com/read/115675/15005150
tdf dynram.tdf
TITLE "DRAM Controller with Refresh (CAS before RAS) and DTACK Generation" ;
-- Version 1.1, 03.02.1998
-- Copyright Frank Rodler
-- You can download it from www.fpga.com.cn or www.pld.com.cn
PA
www.eeworm.com/read/8785/153266
v generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d
www.eeworm.com/read/17812/761342
v generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d
www.eeworm.com/read/17870/763410
v generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d
www.eeworm.com/read/17893/765828
v generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d
www.eeworm.com/read/18104/775042
v generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d
www.eeworm.com/read/18154/777227
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fifo_fpga is
port(
WD : in vl_logic_vector(7 downto 0);
RD : out vl_logic_vector(15 downto 0);
www.eeworm.com/read/18159/777827
v generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d
www.eeworm.com/read/18288/783264
v generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d