代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
代码结果 10,000
www.eeworm.com/read/461671/1551778
extra entries.extra
/disp.v///////
/oc8051_cache_ram.v///////
/oc8051_fpga_top.v////*///
/oc8051_ram.v////*///
/oc8051_rom.v////*///
/read.me////*///
www.eeworm.com/read/461671/1551833
extra entries.extra
/internal.do////*///
/make////*///
/make_fpga////*///
/make_verilog////*///
/oc8051_defines.v////*///
/oc8051_timescale.v////*///
/run////*///
/run_sim.scr////*///
/verilog.log////*///
www.eeworm.com/read/250243/4440755
c usx2yhwdep.c
/*
* Driver for Tascam US-X2Y USB soundcards
*
* FPGA Loader + ALSA Startup
*
* Copyright (c) 2003 by Karsten Wiese
*
* This program is free software; you can redi
www.eeworm.com/read/209559/4972851
c usx2yhwdep.c
/*
* Driver for Tascam US-X2Y USB soundcards
*
* FPGA Loader + ALSA Startup
*
* Copyright (c) 2003 by Karsten Wiese
*
* This program is free software; you can redi
www.eeworm.com/read/190958/5170051
lst netlist.lst
C:\XUP\Markets\PLDs\Workshops\courses\v82_fpga_flow\xupv2pro\labsolutions\verilog\lab3\time_const\loopback.ngc 1155749284
OK
www.eeworm.com/read/190958/5170256
lst netlist.lst
C:\XUP\Markets\PLDs\Workshops\courses\v82_fpga_flow\xupv2pro\labsolutions\vhdl\lab3\time_const\loopback.ngc 1155752236
OK
www.eeworm.com/read/176125/5340078
ml300 readme.ml300
Xilinx ML300 platform
=====================
0. Introduction
---------------
The Xilinx ML300 board is based on the Virtex-II Pro FPGA with
integrated IBM PowerPC 405 core. The board is normally boot
www.eeworm.com/read/342726/3229367
ucf test_dualport.ucf
# XSA Board FPGA pin assignment constraints
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %;
# SDRAM memory tester pin assignments
net
www.eeworm.com/read/342726/3229370
ucf test_dualport.ucf
# XSA Board FPGA pin assignment constraints
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %;
# SDRAM memory tester pin assignments
net
www.eeworm.com/read/342726/3229373
ucf test_dualport.ucf
# XSA Board FPGA pin assignment constraints
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %;
# SDRAM memory tester pin assignments
net