代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
代码结果 10,000
www.eeworm.com/read/439407/6932060
vhd encode_1_msb.vhd
--
-- Module: ENCODE_1_MSB
-- Design: CAM_Top
-- VHDL code: RTL / Combinatorial
--
-- Synthesis Synopsys FPGA Express ver. 3.2
-- Use of "pragma synthesis_off/on" and attributes
--
-- Desc
www.eeworm.com/read/439407/6932066
vhd encode_2_msb.vhd
--
-- Module: ENCODE_2_MSB
-- Design: CAM_Top
-- VHDL code: RTL / Combinatorial
--
-- Synthesis Synopsys FPGA Express ver. 3.2
-- Use of "pragma synthesis_off/on" and attributes
--
-- Desc
www.eeworm.com/read/439407/6932069
vhd encode_4_msb.vhd
--
-- Module: ENCODE_4_MSB
-- Design: CAM_Top
-- VHDL code: RTL / Combinatorial
--
-- Synthesis Synopsys FPGA Express ver. 3.2
-- Use of "pragma synthesis_off/on" and attributes
--
-- Desc
www.eeworm.com/read/267835/6341078
txt readme_430.txt
This archive contains VPR, an FPGA placement and routing tool, and T-VPack,
a program to pack LUTs and flip flops into coarser grained logic blocks and
convert a netlist from blif format to VPR's .net
www.eeworm.com/read/486385/6540856
log automake.log
Started process "Synthesize".
Error running Program:
License checkout: synplifypro
Starting: d:\Program Files\Synplicity\fpga_81\bin\mbin\synplify.exe
Install: d:\Program Files\Synplicity\
www.eeworm.com/read/255611/12068813
edf lab3.edf
(edif lab3
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap
(keywordLevel 0)
)
(status
(written
(timeStamp 1999 7 9 1 52 40)
(program "FPGA Compiler II"
(version
www.eeworm.com/read/340369/12163917
v flowled.v
/*** FPGA开发入门程序---流水灯 ***/
/*** 20080720, by RY *************/
module flowled(led,clk); //模块名flow
output[7:0] led; //定义8个LED输出口
input clk; //
www.eeworm.com/read/18576/794504
dat bookinfo.dat
[General Information]
书名=FPGA原理、设计与应用
作者=
页数=254
SS号=0
下载位置=http://192.168.36.205/01/diskfk/fk86/20/!00001.pdg