encode_1_msb.vhd

Using Block RAM for High-Performance Read.Write Cams

--
-- Module: 	ENCODE_1_MSB
-- Design: 	CAM_Top
-- VHDL code:	RTL / Combinatorial
--
-- Synthesis	Synopsys FPGA Express ver. 3.2 
--		Use of "pragma synthesis_off/on" and attributes
--
-- Description: Encode a 2 bits binary address into 1 bit, map with the LSB address and find if a match occurs
--		if BINARY_ADDR = "10" => MATCH_ADDR = "1" / MATCH_OK = 1 
--		Optional ADDR_VALID = 1 when only one Match (If simultaneous matches can occur)
--		However, the ADDR_VALID generation double the size of the combinatorial logic !
--		if no match found => MATCH_OK = 0 / ADDR_VALID = 0 (MATCH_ADDR is not a valid address)
--		if 2 or more matches found => MATCH_OK = 1 / ADDR_VALID = 0 (MATCH_ADDR is not valid address)
--
--		Choice between GATES ONLY implementation or BUFT implementation. (See comments)
--		Note: Configuration is not supported by synthesis tools
--
-- Device: 	VIRTEX Family (VIRTEX & VIRTEX-E)
--
-- Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
-- Date: July 23, 1999
-- Version: 1.0
--
-- History: 
-- 	1. 
--
--   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

-- Syntax for Synopsys FPGA Express
-- pragma translate_off
--library UNISIM;
--use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on

entity ENCODE_1_MSB is
	port (
	BINARY_ADDR	: in std_logic_vector(1 downto 0);
	ADDR_LSB_0 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_1 	: in std_logic_vector(3 downto 0);
    	MATCH_ADDR	: out std_logic_vector(4 downto 0); -- Match address found
--	ADDR_VALID	: out std_logic; -- '1' if MATCH_ADDR is valid (Only one match)
	MATCH_OK	: out std_logic -- '1' if MATCH found
	);
end ENCODE_1_MSB;

architecture ENCODE_1_MSB_arch of ENCODE_1_MSB is
--
-- Components Declarations:
--
-- Signal Declarations:
-- signal VCC : std_logic;
-- signal GND : std_logic;
--
begin
-- VCC <= '1';
-- GND <= '0';
--
-- Convert the binary address in an address bus, ONLY is ONE match is found
-- Optional ADDR_VALID signal generation double the logic size of the encoder !!!
--
-- Choice between gates only implementation or BUFT implementation.
--
-- Begin GATES ONLY implementation --
GENERATE_MSB_ADDRESS : process (BINARY_ADDR, ADDR_LSB_0, ADDR_LSB_1)
begin
--	Optional -- ADDR_VALID <= '1';
	case BINARY_ADDR(1 downto 0) is	
		when "01" => MATCH_ADDR(4 downto 0)<= '0' & ADDR_LSB_0(3 downto 0);
		when "10" => MATCH_ADDR(4 downto 0)<= '1' & ADDR_LSB_1(3 downto 0);
		when others => 
			MATCH_ADDR(4 downto 0)<= ( others => 'X');										
--	Optional --		ADDR_VALID <= '0';
	end case;
end process GENERATE_MSB_ADDRESS;
-- End GATES ONLY implementation --
--
-- Generate the match signal if one or more matche(s) is/are found
GENERATE_MATCH : process (BINARY_ADDR)
begin
if (BINARY_ADDR = "00") then
	MATCH_OK <= '0';
else
	MATCH_OK <= '1';
end if;
end process GENERATE_MATCH;

end ENCODE_1_MSB_arch;