代码搜索：FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/375904/9344216

vhd i8051_ctr.vhd

-- Modification by Koay Kah Hoe -- Optimize for Xilinx Spartan II FPGA implementation -- Version : 2.9a -- -- Copyright (c) 1999-2001 Tony Givargis. Permission to copy is granted -- provided that thi
·
www.eeworm.com/read/439407/6932062

vhd decode_4.vhd

-- -- Module: DECODE_4 -- Design: CAM_Top -- VHDL code: RTL / Combinatorial -- -- Synthesis Synopsys FPGA Express ver. 3.2 -- Use of "pragma synthesis_off/on" and attributes -- -- Descrip
·
www.eeworm.com/read/439407/6932063

vhd decode_3.vhd

-- -- Module: DECODE_3 -- Design: CAM_Top -- VHDL code: RTL / Combinatorial -- -- Synthesis Synopsys FPGA Express ver. 3.2 -- Use of "pragma synthesis_off/on" and attributes -- -- Descrip
·
www.eeworm.com/read/439407/6932065

vhd decode_1.vhd

-- -- Module: DECODE_1 -- Design: CAM_Top -- VHDL code: RTL / Combinatorial -- -- Synthesis Synopsys FPGA Express ver. 3.2 -- Use of "pragma synthesis_off/on" and attributes -- -- Descrip
·
www.eeworm.com/read/439407/6932071

vhd decode_2.vhd

-- -- Module: DECODE_2 -- Design: CAM_Top -- VHDL code: RTL / Combinatorial -- -- Synthesis Synopsys FPGA Express ver. 3.2 -- Use of "pragma synthesis_off/on" and attributes -- -- Descrip
·
www.eeworm.com/read/443250/7635441

edf add4in.edf

(edif Add4In (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0) ) (status (written (timeStamp 2000 9 19 15 18 53) (program "FPGA Express" (version
·
www.eeworm.com/read/309739/13665108

txt ram_readme.txt

The following files were generated for 'ram' in directory D:\Develop\PQS\FPGA\fft_test: ram.edn: Electronic Data Netlist (EDN) file containing the information required to implement the mo
·
www.eeworm.com/read/476107/6763078

txt uart.vhd.txt

------------------------------- --uart send & recive for FPGA -- 2009 ------------------------------- LIBRARY ieee; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_arith.ALL; USE IEEE.STD_LOG
·
www.eeworm.com/read/476110/6763081

txt uart.txt

------------------------------- --uart send & recive for FPGA -- 2009 ------------------------------- LIBRARY ieee; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_arith.ALL; USE IEEE.STD_LOG
·
www.eeworm.com/read/17546/737923

v video.v

// FPGA PACMAN video hardware // // Version : beta2 // // Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved // // Important ! // // This program is freeware for non-commercial use.
·