代码搜索:FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

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fc2 vhdl.fc2

#---------------------------------------------------------- # Synopsys FPGA Compiler II VHDL simulation script vhdl.fc2 # for the book: DSP with FPGAs (2. edition) # Author-EMAIL: Uwe.Meyer-Baese@
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fc2 verilog.fc2

#---------------------------------------------------------- # Synopsys FPGA Compiler II simulation script verilog.fc2 # for the book: DSP with FPGAs (2. edition) # Author-EMAIL: Uwe.Meyer-Baese@ie
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v comp42_n64.v

`timescale 1ns/10ps /*----------------------------------------------------------------------------- $RCSfile: & $Source: /home/lefurgy/tmp/ISC-repository/isc/hardware/ARM10/behavioral/pipelined/fpga2/
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txt sram_ctrl_readme.txt

The following files were generated for 'sram_ctrl' in directory E:\modulator\modulator_fpga\modulator: sram_ctrl.mif: Memory Initialization File which is automatically generated by the CO
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c nandtest.c

/*************************************************************** Copyright(c) 2002 VIA Technologies, Inc. All Rights Reserved. Filename: Main.C Description: platform : fpga_top.5-2-19-18.bit
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vhd i8051_all.vhd

-- Modification by Koay Kah Hoe -- Optimize for Xilinx Spartan II FPGA implementation -- Version : 2.9a -- -- -- Copyright (c) 1999-2001 Tony Givargis. Permission to copy is granted -- provided that
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v comp42_n64.v

`timescale 1ns/10ps /*----------------------------------------------------------------------------- $RCSfile: & $Source: /home/lefurgy/tmp/ISC-repository/isc/hardware/ARM10/behavioral/pipelined/fpga2/
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v parameters.v

// // Module: parameters // Design: CAM_Top // Verilog code: Defines Parameters for CAM design // // Synthesis_tool Synopsys FPGA Express ver. 3.2 - Option = Preserve Hierarchy // En
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asm test.asm

; http://gforge.openchip.org/projects/a86 ; ; First Program being assembled and executed on a86 (FPGA implementation) ; (earlier it was only either simulation run or machine code programs) ; ; In