代码搜索:FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

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fc2 verilog.fc2

#---------------------------------------------------------- # Synopsys FPGA Compiler II simulation script verilog.fc2 # for the book: DSP with FPGAs (2. edition) # Author-EMAIL: Uwe.Meyer-Baese@ie
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fc2 verilog.fc2

#---------------------------------------------------------- # Synopsys FPGA Compiler II simulation script verilog.fc2 # for the book: DSP with FPGAs (2. edition) # Author-EMAIL: Uwe.Meyer-Baese@ie
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bat make_rom.bat

@echo off rem rem ALTERA FPGA-PACMAN ROM builder rem echo ---------- build PROM data ---------- rem 0000 1000 2000 3000 4000 5000 6000 7000
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v venc_vga8.v

// // FPGA PACMAN "VGA 8BPP" video encoder for ALTERA CYCLONE // // Version : // // Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved // // Important ! // // This program is free
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fc2 verilog.fc2

#---------------------------------------------------------- # Synopsys FPGA Compiler II simulation script verilog.fc2 # for the book: DSP with FPGAs (2. edition) # Author-EMAIL: Uwe.Meyer-Baese@ie
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fc2 vhdl.fc2

#---------------------------------------------------------- # Synopsys FPGA Compiler II VHDL simulation script vhdl.fc2 # for the book: DSP with FPGAs (2. edition) # Author-EMAIL: Uwe.Meyer-Baese@
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fc2 vhdl.fc2

#---------------------------------------------------------- # Synopsys FPGA Compiler II VHDL simulation script vhdl.fc2 # for the book: DSP with FPGAs (2. edition) # Author-EMAIL: Uwe.Meyer-Baese@
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c 陀螺仪传感器融合_code例程.c

/* * Self-balancing Ctrl * * By DDAI * 2010.03.21 */ #include "system.h" //FPGA NIOS II 软核头文件 #include "sys/alt_irq.h" #incl
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edf compare.edf

(edif COMPARE (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0) ) (status (written (timeStamp 2002 7 25 13 4 43) (program "FPGA Express" (version
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edf ex4_2.edf

(edif COMPARE (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0) ) (status (written (timeStamp 2002 7 25 13 4 43) (program "FPGA Express" (version