venc_vga8.v

DE1-FPGA-Board

//
// FPGA PACMAN "VGA 8BPP" video encoder for ALTERA CYCLONE
//
// Version : 
//
// Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved
// 
// Important !
//
// This program is freeware for non-commercial use. 
// An author does no guarantee about this program.
// You can use this under your own risk. 
//
// 2003. 2.17 rebuild from 'dblscan.v'
// 2003. 5. 8 Altera FPGA modification by Katsumi Degawa
//

module venc(
  pclk,dclk,rgb8_in,hs_in,vs_in,
  r_out,g_out,b_out,
  hs_out,vs_out
);
// input signals
input pclk;             // 6.144MHz  input pixel clock
input dclk;             // 12.288Mhz output pixel clock
input [7:0] rgb8_in;    // RGB   input
input hs_in;            // HSYNC input (16KHz)
input vs_in;            // VSYNC input (60Hz)

// output signals
output [2:0] r_out,g_out;// R,G,B output level
output [1:0] b_out; 	 //
output hs_out;           // HSYNC output
output vs_out;           // VSYNC output

//---------------------------------------------------------------------------
// setup parameter
//---------------------------------------------------------------------------

parameter H_COUNT = 384; // number of pixels in H-SCAN
parameter HS_POS  = 16;  // HSYNC position 
parameter HS_COUNT= 8;   // HSYNC width / pixel
parameter VS_COUNT= 8;   // VSYNC width / HSYNC_OUT

//---------------------------------------------------------------------------
// input timming
//---------------------------------------------------------------------------
reg [8:0] hpos_i;    // input capture postion
reg ihs;
wire ic_raise = ~ihs&hs_in; // raise hsync
always @(posedge pclk)
begin
	hpos_i <= ic_raise ? 0 : hpos_i + 1;
	ihs =  hs_in;
end

//---------------------------------------------------------------------------
//output timming
//---------------------------------------------------------------------------
reg [8:0] hpos_o;
reg ohs , hsync_o;
wire oh_raise = ~ohs&hs_in; // raise hsync 
wire oh_return = oh_raise | (hpos_o == H_COUNT-1);
always @(posedge dclk)
begin
	hpos_o <= oh_return ? 0 : hpos_o + 1;
	ohs <= hs_in;

	// remake HSYNC
	if(hpos_o == HS_POS)
	begin
		hsync_o <= 1'b1;
	end
	if(hpos_o == (HS_POS+HS_COUNT) )
		hsync_o <= 1'b0;
end

//---------------------------------------------------------------------------
// RGB capture(portA) & output(portB)
//---------------------------------------------------------------------------
wire [7:0] rgb8_out;  // RGB output

alt_ram_512_8_8 double_scan_ram(
.wrclock(pclk),
.wraddress(hpos_i),
.data(rgb8_in),
.wren(1'b1),
.rdclock(dclk),
.rdaddress(hpos_o),
.q(rgb8_out)
);

//---------------------------------------------------------------------------
// vsync remake
//
// 1 HSYNC_IN delay & HSYNC pulse width = 4xHSYNC(in)
//---------------------------------------------------------------------------

reg [2:0] vs_cnt;
reg vsync_o;

always @(posedge hsync_o)
begin
	if(~vs_in)
	begin
		vs_cnt <= VS_COUNT-1;
		vsync_o <= 1;
	end else begin
		if(vs_cnt==0)
			vsync_o <= 0;
 	   	vs_cnt <= vs_cnt - 1;
	end
end

//---------------------------------------------------------------------------
// output
//---------------------------------------------------------------------------
assign r_out = { rgb8_out[7:5] };  // 470ohm,1Kohm,2Kohm
assign g_out = { rgb8_out[4:2] };  // 470ohm,1Kohm,2Kohm
assign b_out = { rgb8_out[1:0] };  // 470ohm,1Kohm

// converted SYNC signal
assign vs_out = ~vsync_o;
assign hs_out = ~hsync_o;

endmodule