代码搜索：FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/427629/1969131

_info

m255 13 cModel Technology dE:\farsight_fpga_course\code\high\onchip ram\quartus\simulation\modelsim va_graycounter I^2Zf5mVNijM7az`Un[kL=0 VMk:N^O83OA1@aDzHMfGYh3 dE:\farsight_fpga_course\code\high\on
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www.eeworm.com/read/427629/1969252

xrf ram_control_modelsim.xrf

vendor_name = ModelSim source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/test1/RAM_36.v source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/test1/ram_control.v source_file = 1
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www.eeworm.com/read/355352/3054573

ref hdpdeps.ref

V3 3 FL D:/usb/FPGA_CPLD/USB_TEST/usbtest.vhd 2008/08/22.14:26:02 I.24 EN work/usbtest 1220499205 FL D:/usb/FPGA_CPLD/USB_TEST/usbtest.vhd \ PB ieee/std_logic_1164 1131108373 PB ieee/
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www.eeworm.com/read/351002/3112241

prj updwnlo4.prj

Created by PCM: 3/5/102 Empty design C:\FPGA\UPDWNLO4\UPDWNLO4\updwnlo4.EDF created: 3/5/102 [14.1.40]. '' saved on 02/03/05 14:11 'C:\FPGA\UPDWNLO4\UPDWNLO4\UPDWNLO4.vhd' saved on 02/03/05 14:17
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www.eeworm.com/read/351002/3112590

prj srllo8.prj

Created by PCM: 3/5/102 Empty design C:\FPGA\SRLLO8\SRLLO8\srllo8.EDF created: 3/5/102 [17.14.57]. '' saved on 02/03/05 17:23 Document c:\fpga\srllo8\srllo8\srllo8.vhd added: 3/5/102 [17.23.46]. I
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www.eeworm.com/read/34184/1039432

c 7455.c

/*********************************************/ /*程序功能：飞思卡尔加速度传感器MMA7455娱乐仪*/ /*程序模块：1、LED阵列显示模块 */ /* 2、1602显示模块 */ /* 3、I2C通信模块
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www.eeworm.com/read/34231/1039837

c 7455.c

/*********************************************/ /*程序功能：飞思卡尔加速度传感器MMA7455娱乐仪*/ /*程序模块：1、LED阵列显示模块 */ /* 2、1602显示模块 */ /* 3、I2C通信模块
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www.eeworm.com/read/291453/8417590

vhd 相应加法器的测试向量（test bench).vhd

-- download from: www.pld.com.cn & www.fpga.com.cn entity testbench is end; ------------------------------------------------------------------------ -- testbench for 8-bit adder ------------
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www.eeworm.com/read/284640/8912184

txt 相应加法器的测试向量（test bench).txt

-- download from: www.pld.com.cn & www.fpga.com.cn entity testbench is end; ------------------------------------------------------------------------ -- testbench for 8-bit adder ------------
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www.eeworm.com/read/169584/9849719

h usbotg_internal.h

/********** Macro definition for SW level**********************************/ //#define PRINT //#define Tahiti //#define FPGA //#define NOLM //#define UartTest //Uart test only (5 polling times)
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