代码搜索:FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

代码结果 10,000
www.eeworm.com/read/281488/9153050

c fpga-test.c

/* fpga-test.c, need insmod s3c2410-fpga.o first. author: wb date: 2005-6-13 21:05 */ #include #include #include #include
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pdf fpga_design.pdf

www.eeworm.com/read/377792/9262489

c fpga-test.c

/* fpga-test.c, need insmod s3c2410-fpga.o first. author: wb date: 2005-6-13 21:05 */ #include #include #include #include
www.eeworm.com/read/376804/9305984

v fpga_transmitter.v

// RS-232 TX module // (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006 //`define DEBUG // in DEBUG mode, we output one bit per clock cycle (useful for faster simulations) module uart_trans
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qsf fpga_uartrw.qsf

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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v fpga_receiver.v

// RS-232 RX module // (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006 module uart_receiver(clk, RxD, RxD_data_ready, RxD_data); input clk, RxD; output RxD_data_ready; // onc clock pulse whe
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tcl fpga_uartrw.tcl

# Setup pin setting for EP2C5_EP2C8 main board set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF set_location_assi
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jdi fpga_uartrw.jdi

www.eeworm.com/read/376804/9306005

done fpga_uartrw.done

Wed May 07 10:10:09 2008