代码搜索：FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/428615/8855562

srm nandflash.srm

f "noname"; #file 0 f "d:\synplicity\fpga_85\lib\vhd\std.vhd"; #file 1 f "d:\synplicity\nandflash\nandflash.vhd"; #file 2 f "d:\synplicity\fpga_85\lib\vhd\std1164.vhd"; #file 3 f "d:\synplicity\fp
·
www.eeworm.com/read/379202/9204698

srd flift.srd

f "noname"; #file 0 f "d:\program files\synplicity\fpga_862\lib\vhd\std.vhd"; #file 1 f "e:\my synplyfy\lift\flift.vhd"; #file 2 f "d:\program files\synplicity\fpga_862\lib\vhd\std1164.vhd"; #file
·
www.eeworm.com/read/462151/7208424

c 485-test.c

/* fpga-test.c, need insmod s3c2410-fpga.o first. author: wb date: 2005-6-13 21:05 */ #include #include #include #include
·
www.eeworm.com/read/17670/752660

prj lvds_bist_top_vhdl.prj

vhdl work "E:\linpingping\ATCA_converge_board\LVDS_Serdes_list_FPGA1\seven_bit_reg_w_ce.vhd" vhdl work "E:\linpingping\ATCA_converge_board\LVDS_Serdes_list_FPGA1\count_to_16x.vhd" vhdl work "E:\linp
·
www.eeworm.com/read/17670/752778

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\par.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -w -intstyle ise -ol std -t 1 lvds_bist_top_map.ncd lvds_bist_to
·
www.eeworm.com/read/17670/752779

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\bitgen.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -f lvds_bist_top.ut lvds_bist_top.ncd s FormatS
·
www.eeworm.com/read/17670/752780

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -dd _ngo -nt timestamp -i -p xc5vfx130t-ff173
·
www.eeworm.com/read/17694/754237

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise -intstyle ise -dd _ngo -nt timestamp -i -p xc5vfx130t-
·
www.eeworm.com/read/17761/756999

xrf ram_control_modelsim.xrf

vendor_name = ModelSim source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/test/RAM_36.v source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v source_file = 1,
·
www.eeworm.com/read/18256/782677

fes pex.fes

create_project FPGA create_library system create_library pex_lib create_library arm add_file -library system -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/xilinx_pkg.vhd add_file
·