代码搜索：Events

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events

# IA-64 Itanium 2 events # IA64_2 Basic Events, Table 11-1 event:0x12 counters:0,1,2,3 um:zero minimum:500 name:CPU_CYCLES : CPU Cycles event:0x08 counters:0,1,2,3 um:zero minimum:500 name:IA64_INST_
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events

# ARM V6 events # event:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses event:0x01 counters:0,1 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles i
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events

# XScale 2 events # event:0x00 counters:1,2,3,4 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses event:0x01 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL
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events

# XScale 1 events # event:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses event:0x01 counters:1,2 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles
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events

# MPCore events # event:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses event:0x01 counters:0,1 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles i
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events

#ppc64 Cell Broadband Engine events # # Copyright OProfile authors # #(C) COPYRIGHT International Business Machines Corp. 2006 # Contributed by Maynard Johnson # # # As many as
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events

#PPC64 POWER5 events # # Within each group the event names must be unique. Each event in a group is # assigned to a unique counter. The groups are from the groups defined in the # Performance Mon
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events

# ppc64 pa6t events # # Unlike the IBM ppc64 chips, any of pa6t's events can be programmed into any # of the counters (pmc2-5). The notion of groups on pa6t is thus # artificial. That said, we can sti
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events

#PPC64 POWER5++ events # # Copyright OProfile authors # Copyright (c) International Business Machines, 2007. # Contributed by Maynard Johnson . # # # Within each group the event
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events

#PPC64 PowerPC970 events # # Within each group the event names must be unique. Each event in a group is # assigned to a unique counter. The groups are from the groups defined in the # Performance
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