events

跨平台性能调试工具

#PPC64 POWER5 events
#
#  Within each group the event names must be unique.  Each event in a group is
#  assigned to a unique counter.  The groups are from the groups defined in the
#  Performance Monitor Unit user guide for this processor.
#
#  Only events within the same group can be selected simultaneously.
#  Each event is given a unique event number.  The event number is used by the
#  OProfile code to resolve event names for the post-processing.  This is done
#  to preserve compatibility with the rest of the OProfile code.  The event
#  numbers are formatted as follows: <group_num>concat(<counter for the event>).

#Group Default
event:0X001 counters:3 um:zero minimum:10000 name:CYCLES : Processor Cycles using continuous sampling

#Group 0 with random sampling
event:0X002 counters:2 um:zero minimum:10000 name:CYCLES_RND_SMPL : Processor Cycles with random sampling


#Group 1 pm_utilization, CPI and utilization data
event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
event:0X011 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP1 : (Group 1 pm_utilization) IOPS instructions completed
event:0X012 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP1 : (Group 1 pm_utilization) Instructions dispatched
event:0X013 counters:3 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor cycles
event:0X014 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_utilization) Instructions completed
event:0X015 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles

#Group 2 pm_completion, Completion and cycle counts
event:0X020 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP2 : (Group 2 pm_completion) One or more PPC instruction completed
event:0X021 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP2 : (Group 2 pm_completion) Cycles GCT empty
event:0X022 counters:2 um:zero minimum:1000 name:PM_GRP_CMPL_GRP2 : (Group 2 pm_completion) Group completed
event:0X023 counters:3 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_completion) Processor cycles
event:0X024 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP2 : (Group 2 pm_completion) Instructions completed
event:0X025 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP2 : (Group 2 pm_completion) Run cycles

#Group 3 pm_group_dispatch, Group dispatch events
event:0X030 counters:0 um:zero minimum:1000 name:PM_GRP_DISP_VALID_GRP3 : (Group 3 pm_group_dispatch) Group dispatch valid
event:0X031 counters:1 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP3 : (Group 3 pm_group_dispatch) Group dispatch rejected
event:0X032 counters:2 um:zero minimum:1000 name:PM_GRP_DISP_BLK_SB_CYC_GRP3 : (Group 3 pm_group_dispatch) Cycles group dispatch blocked by scoreboard
event:0X033 counters:3 um:zero minimum:1000 name:PM_INST_DISP_GRP3 : (Group 3 pm_group_dispatch) Instructions dispatched
event:0X034 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP3 : (Group 3 pm_group_dispatch) Instructions completed
event:0X035 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP3 : (Group 3 pm_group_dispatch) Run cycles

#Group 4 pm_clb1, CLB fullness
event:0X040 counters:0 um:zero minimum:1000 name:PM_0INST_CLB_CYC_GRP4 : (Group 4 pm_clb1) Cycles no instructions in CLB
event:0X041 counters:1 um:zero minimum:1000 name:PM_2INST_CLB_CYC_GRP4 : (Group 4 pm_clb1) Cycles 2 instructions in CLB
event:0X042 counters:2 um:zero minimum:1000 name:PM_CLB_EMPTY_CYC_GRP4 : (Group 4 pm_clb1) Cycles CLB empty
event:0X043 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_MOD_CYC_GRP4 : (Group 4 pm_clb1) Marked load latency from L3.5 modified
event:0X044 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP4 : (Group 4 pm_clb1) Instructions completed
event:0X045 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP4 : (Group 4 pm_clb1) Run cycles

#Group 5 pm_clb2, CLB fullness
event:0X050 counters:0 um:zero minimum:1000 name:PM_5INST_CLB_CYC_GRP5 : (Group 5 pm_clb2) Cycles 5 instructions in CLB
event:0X051 counters:1 um:zero minimum:1000 name:PM_6INST_CLB_CYC_GRP5 : (Group 5 pm_clb2) Cycles 6 instructions in CLB
event:0X052 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_SRQ_INST_VALID_GRP5 : (Group 5 pm_clb2) Marked instruction valid in SRQ
event:0X053 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP5 : (Group 5 pm_clb2) IOPS instructions completed
event:0X054 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP5 : (Group 5 pm_clb2) Instructions completed
event:0X055 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP5 : (Group 5 pm_clb2) Run cycles

#Group 6 pm_gct_empty, GCT empty reasons
event:0X060 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_CYC_GRP6 : (Group 6 pm_gct_empty) Cycles no GCT slot allocated
event:0X061 counters:1 um:zero minimum:1000 name:PM_GCT_NOSLOT_IC_MISS_GRP6 : (Group 6 pm_gct_empty) No slot in GCT caused by I cache miss
event:0X062 counters:2 um:zero minimum:1000 name:PM_GCT_NOSLOT_SRQ_FULL_GRP6 : (Group 6 pm_gct_empty) No slot in GCT caused by SRQ full
event:0X063 counters:3 um:zero minimum:1000 name:PM_GCT_NOSLOT_BR_MPRED_GRP6 : (Group 6 pm_gct_empty) No slot in GCT caused by branch mispredict
event:0X064 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP6 : (Group 6 pm_gct_empty) Instructions completed
event:0X065 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP6 : (Group 6 pm_gct_empty) Run cycles

#Group 7 pm_gct_usage, GCT Usage
event:0X070 counters:0 um:zero minimum:1000 name:PM_GCT_USAGE_00to59_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT less than 60% full
event:0X071 counters:1 um:zero minimum:1000 name:PM_GCT_USAGE_60to79_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT 60-79% full
event:0X072 counters:2 um:zero minimum:1000 name:PM_GCT_USAGE_80to99_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT 80-99% full
event:0X073 counters:3 um:zero minimum:1000 name:PM_GCT_FULL_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT full
event:0X074 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP7 : (Group 7 pm_gct_usage) Instructions completed
event:0X075 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP7 : (Group 7 pm_gct_usage) Run cycles

#Group 8 pm_lsu1, LSU LRQ and LMQ events
event:0X080 counters:0 um:zero minimum:1000 name:PM_LSU_LRQ_S0_ALLOC_GRP8 : (Group 8 pm_lsu1) LRQ slot 0 allocated
event:0X081 counters:1 um:zero minimum:1000 name:PM_LSU_LRQ_S0_VALID_GRP8 : (Group 8 pm_lsu1) LRQ slot 0 valid
event:0X082 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP8 : (Group 8 pm_lsu1) LMQ slot 0 allocated
event:0X083 counters:3 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP8 : (Group 8 pm_lsu1) LMQ slot 0 valid
event:0X084 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP8 : (Group 8 pm_lsu1) Instructions completed
event:0X085 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP8 : (Group 8 pm_lsu1) Run cycles

#Group 9 pm_lsu2, LSU SRQ events
event:0X090 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_S0_ALLOC_GRP9 : (Group 9 pm_lsu2) SRQ slot 0 allocated
event:0X091 counters:1 um:zero minimum:1000 name:PM_LSU_SRQ_S0_VALID_GRP9 : (Group 9 pm_lsu2) SRQ slot 0 valid
event:0X092 counters:2 um:zero minimum:1000 name:PM_LSU_SRQ_SYNC_CYC_GRP9 : (Group 9 pm_lsu2) SRQ sync duration
event:0X093 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_FULL_CYC_GRP9 : (Group 9 pm_lsu2) Cycles SRQ full
event:0X094 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP9 : (Group 9 pm_lsu2) Instructions completed
event:0X095 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP9 : (Group 9 pm_lsu2) Run cycles

#Group 10 pm_lsu3, LSU SRQ and LMQ events
event:0X0A0 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_STFWD_GRP10 : (Group 10 pm_lsu3) SRQ store forwarded
event:0X0A1 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP10 : (Group 10 pm_lsu3) Cycles LMQ and SRQ empty
event:0X0A2 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_LHR_MERGE_GRP10 : (Group 10 pm_lsu3) LMQ LHR merges
event:0X0A3 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_CYC_GRP10 : (Group 10 pm_lsu3) Cycles SRQ empty
event:0X0A4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP10 : (Group 10 pm_lsu3) Instructions completed
event:0X0A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP10 : (Group 10 pm_lsu3) Run cycles

#Group 11 pm_prefetch1, Prefetch stream allocation
event:0X0B0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP11 : (Group 11 pm_prefetch1) Instructions fetched missed L2
event:0X0B1 counters:1 um:zero minimum:1000 name:PM_INST_FETCH_CYC_GRP11 : (Group 11 pm_prefetch1) Cycles at least 1 instruction fetched
event:0X0B2 counters:2 um:zero minimum:1000 name:PM_DC_PREF_STREAM_ALLOC_BLK_GRP11 : (Group 11 pm_prefetch1) D cache out of prefech streams
event:0X0B3 counters:3 um:zero minimum:1000 name:PM_DC_PREF_STREAM_ALLOC_GRP11 : (Group 11 pm_prefetch1) D cache new prefetch stream allocated
event:0X0B4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP11 : (Group 11 pm_prefetch1) Instructions completed
event:0X0B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP11 : (Group 11 pm_prefetch1) Run cycles

#Group 12 pm_prefetch2, Prefetch events
event:0X0C0 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP12 : (Group 12 pm_prefetch2) IOPS instructions completed
event:0X0C1 counters:1 um:zero minimum:1000 name:PM_CLB_FULL_CYC_GRP12 : (Group 12 pm_prefetch2) Cycles CLB full
event:0X0C2 counters:2 um:zero minimum:1000 name:PM_L1_PREF_GRP12 : (Group 12 pm_prefetch2) L1 cache data prefetches
event:0X0C3 counters:3 um:zero minimum:1000 name:PM_IC_PREF_INSTALL_GRP12 : (Group 12 pm_prefetch2) Instruction prefetched installed in prefetch
event:0X0C4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP12 : (Group 12 pm_prefetch2) Instructions completed
event:0X0C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP12 : (Group 12 pm_prefetch2) Run cycles

#Group 13 pm_prefetch3, L2 prefetch and misc events
event:0X0D0 counters:0 um:zero minimum:1000 name:PM_LSU_BUSY_REJECT_GRP13 : (Group 13 pm_prefetch3) LSU busy due to reject
event:0X0D1 counters:1 um:zero minimum:1000 name:PM_1INST_CLB_CYC_GRP13 : (Group 13 pm_prefetch3) Cycles 1 instruction in CLB
event:0X0D2 counters:2 um:zero minimum:1000 name:PM_L2_PREF_GRP13 : (Group 13 pm_prefetch3) L2 cache prefetches
event:0X0D3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP13 : (Group 13 pm_prefetch3) IOPS instructions completed
event:0X0D4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP13 : (Group 13 pm_prefetch3) Instructions completed
event:0X0D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP13 : (Group 13 pm_prefetch3) Run cycles

#Group 14 pm_prefetch4, Misc prefetch and reject events
event:0X0E0 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_SRQ_LHS_GRP14 : (Group 14 pm_prefetch4) LSU0 SRQ rejects
event:0X0E1 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_SRQ_LHS_GRP14 : (Group 14 pm_prefetch4) LSU1 SRQ rejects
event:0X0E2 counters:2 um:zero minimum:1000 name:PM_DC_PREF_DST_GRP14 : (Group 14 pm_prefetch4) DST (Data Stream Touch) stream start
event:0X0E3 counters:3 um:zero minimum:1000 name:PM_L2_PREF_GRP14 : (Group 14 pm_prefetch4) L2 cache prefetches
event:0X0E4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP14 : (Group 14 pm_prefetch4) Instructions completed
event:0X0E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP14 : (Group 14 pm_prefetch4) Run cycles

#Group 15 pm_lsu_reject1, LSU reject events
event:0X0F0 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_ERAT_MISS_GRP15 : (Group 15 pm_lsu_reject1) LSU reject due to ERAT miss