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embedded_rom.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = G:\8086vga
SET speedgrade = -4
SET simulationfiles = Behavioral
SET asysymbol =
embedded_rom.vhd
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
embedded_rom.edn
(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2007 8 15 9 43 34)
(author "Xilinx, Inc.")
(program "Xilinx CORE Generator" (version "Xi
embedded_rom.vho
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
embedded_rom.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
embedded_rom.mif
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embedded_rom.sym
VERSION 5
BEGIN SYMBOL embedded_rom
SYMBOLTYPE BLOCK
TIMESTAMP 2007 8 15 1 43 18
SYMPIN 0 80 Input a[7:0]
SYMPIN 0 304 Input clk
SYMPIN 288 80 Output spo[7:0]
BEGIN DISPLAY 32 32 TEXT embedded_
embedded_rom.asy
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 embedded_rom
RECTANGLE Normal 32 32 256 544
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName a[7:0]
PINATTR Polarity IN
LINE Normal 0 304 32 304
PIN 0
embedded_rom.veo
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,