embedded_rom.v

：两人乒乓球赛 Requires: D2SB and DIO4 with VGA monitor and PS2 Keyboard

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// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file embedded_rom.v when simulating
// the core, embedded_rom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module embedded_rom(
	a,
	clk,
	spo);


input [7 : 0] a;
input clk;
output [7 : 0] spo;

// synopsys translate_off

      DIST_MEM_GEN_V3_2 #(
		8,	// c_addr_width
		"0",	// c_default_data
		256,	// c_depth
		1,	// c_has_clk
		0,	// c_has_d
		0,	// c_has_dpo
		0,	// c_has_dpra
		0,	// c_has_i_ce
		0,	// c_has_qdpo
		0,	// c_has_qdpo_ce
		0,	// c_has_qdpo_clk
		0,	// c_has_qdpo_rst
		0,	// c_has_qdpo_srst
		0,	// c_has_qspo
		0,	// c_has_qspo_ce
		0,	// c_has_qspo_rst
		0,	// c_has_qspo_srst
		1,	// c_has_spo
		0,	// c_has_spra
		0,	// c_has_we
		"embedded_rom.mif",	// c_mem_init_file
		0,	// c_mem_type
		0,	// c_pipeline_stages
		0,	// c_qce_joined
		0,	// c_qualify_we
		1,	// c_read_mif
		1,	// c_reg_a_d_inputs
		0,	// c_reg_dpra_input
		1,	// c_sync_enable
		8)	// c_width
	inst (
		.A(a),
		.CLK(clk),
		.SPO(spo),
		.D(),
		.DPRA(),
		.SPRA(),
		.WE(),
		.I_CE(),
		.QSPO_CE(),
		.QDPO_CE(),
		.QDPO_CLK(),
		.QSPO_RST(),
		.QDPO_RST(),
		.QSPO_SRST(),
		.QDPO_SRST(),
		.DPO(),
		.QSPO(),
		.QDPO());


// synopsys translate_on

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of embedded_rom is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of embedded_rom is "black_box"

endmodule