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EEPROM 的代码
debug.lkv
-z -q -c -heap0x400 -m"./Debug/SEEDVPM642eepromw.map" -o"./Debug/SEEDVPM642eepromw.out" -stack0x400 -w -x -i"c:/tic6000v2.20.18/c6000/bios/lib" -i"c:/tic6000v2.20.18/c6000/rtdx/lib" -i"c:/tic6000v2.20
seedvpm642eepromr.pjt
; Code Composer Project File, Version 2.0 (do not modify or remove this line)
[Project Settings]
ProjectDir="C:\tic6000v2.20.18\myprojects\SEEDVPM642_example_new\SEEDVPM642_eeprom\"
ProjectType=E
seedvpm642eepromw.pjt
; Code Composer Project File, Version 2.0 (do not modify or remove this line)
[Project Settings]
ProjectDir="C:\tic6000v2.20.18\myprojects\SEEDVPM642_example_new\SEEDVPM642_eeprom\"
ProjectType=E
program.bat
@echo off
echo WiiKey(1.9s)-Auto-Flasher for ATMega8 (Super Smash Brothers Brawl Original Disc Fix)
echo.
echo.
echo.
avrdude -p m8 -c sp12 -U flash:w:wiikey19s.hex -U lfuse:w:0xE4:m -U hfu
rtc8025.h
#define false2 0
#define true2 1
#define writeadder 0x64 //rtc read address
#define readadder 0x65 //rtc write address
//unsigned char rtc8025_timevalue[8];
char iic2_buf;
struct bit_iic2
rp6control_04_externaleeprom.c
/*
* ****************************************************************************
* RP6 ROBOT SYSTEM - RP6 CONTROL M32 Examples
* ***************************************************************
top.v.bak
`include "./signal.v"
`include"./EEPROM.v"
`include "./EEPROM_WR.v"
`timescale 1ns/1ns
module Top;
wire RESET;
wire CLK;
wire RD,WR;
wire ACK;
wire[10:0] ADDR;
wire[7:0] DATA;
wire SCL;
wire SDA;
Sign
signal
`timescale 1ns/1ns
`difine timeslice 200
module Signal(RESET,CLK,RD,WR,ADDR,ACK,DATA);
output RESET;
output CLK;
output RD,WR;
output[10:0]ADDR;
input ACK;
inout[7:0] DATA;
reg RESET;
reg CLK;`timesca
top.v
`include "./signal.v"
`include"./EEPROM.v"
`include "./EEPROM_WR.v"
`timescale 1ns/1ns
module Top;
wire RESET;
wire CLK;
wire RD,WR;
wire ACK;
wire[10:0] ADDR;
wire[7:0] DATA;
wire SCL;
wire SDA;
Sign
signal.bak
`timescale 1ns/1ns
`difine timeslice 200
module Signal(RESET,CLK,RD,WR,ADDR,ACK,DATA);
output RESET;
output CLK;
output RD,WR;
output[10:0]ADDR;
input ACK;
inout[7:0] DATA;
reg RESET;
reg CLK;`timesca