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digital_voltmeter.mrp
Release 7.1.01i Map H.39
Xilinx Mapping Report File for Design 'digital_voltmeter'
Design Information
------------------
Command Line : E:/Program/EDA/Xilinx/bin/nt/map.exe -ise
e:\demo_fpga\DEMO_
digital_voltmeter.pcf
//! **************************************************************************
// Written by: Map H.39 on Thu Mar 24 23:25:30 2005
//! ***************************************************************
digital_clk.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:45:29 03/25/05
-- Design Name:
-- Module Name: digital_
digital_clk.par
Release 7.1.01i par H.39
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
HXS:: Fri Mar 25 03:07:58 2005
par -w -intstyle ise -ol std -t 1 digital_clk_map.ncd digital_clk.ncd
digital_clk
digital clock (2).opt
### uVision2 Project, (C) Keil Software
### Do not modify !
cExt (*.c)
aExt (*.s*; *.src; *.a*)
oExt (*.obj)
lExt (*.lib)
tExt (*.txt; *.h; *.inc)
pExt (*.plm)
CppX (*.cpp)
DaveTm {
digital clock (2).plg
礦ision3 Build Log
Project:
F:\Proteus书稿\MCS-51 Demonstration\Chapter 8\62 Digital Clock (2)\Digital Clock (2).uv2
Project File Date: 08/04/2006
Outp
digital clock (2).asm
S_SET BIT P1.0 ;数字钟秒控制位
M_SET BIT P1.1 ;分钟控制位
H_SET BIT P1.2 ;小时控制位
SECOND EQU 30H
MINUTE EQU 31H
HOUR EQU 32H
TCNT EQU 34H
ORG 00H
SJMP START
ORG 0BH
LJMP IN