digital_clk.vhd

总体演示程序DEMO_FPGA.rar

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-- Company: 
-- Engineer:
--
-- Create Date:    00:45:29 03/25/05
-- Design Name:    
-- Module Name:    digital_clk - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity digital_clk is
    Port ( clk : in std_logic;
           ireset : in std_logic;
           oh : out std_logic_vector(7 downto 0);
           om : out std_logic_vector(7 downto 0);
           os : out std_logic_vector(7 downto 0));
end digital_clk;

architecture Behavioral of digital_clk is

signal sclka,sclkb : std_logic;
begin
process(clk,ireset)
variable c : std_logic_vector(3 downto 0);
variable d : std_logic_vector(3 downto 0);
begin
   if ireset='1' then c:="0000";d:="0000";
   elsif rising_edge(clk) then 
      if c<"1001" then c:=c+1;
	 else c:="0000";
	   if d<"0101" then d:=d+1;sclka<='0';
	   else d:="0000";sclka<='1';
	   end if;
      end if;
   end if;
   os<=d&c;
end process;

process(sclka,ireset)
variable c : std_logic_vector(3 downto 0);
variable d : std_logic_vector(3 downto 0);
begin
   if ireset='1' then c:="0000";d:="0000";
   elsif rising_edge(sclka) then 
      if c<"1001" then c:=c+1;
	 else c:="0000";
	   if d<"0101" then d:=d+1;sclkb<='0';
	   else d:="0000";sclkb<='1';
	   end if;
      end if;
   end if;
   om<=d&c;
end process;
 
process(sclkb,ireset)
variable c : std_logic_vector(3 downto 0);
variable d : std_logic_vector(3 downto 0);
begin
   if ireset='1' then c:="0000";d:="0000";
   elsif rising_edge(sclkb) then 
      if c="0010" then 
	    if d<"0011" then d:=d+1;
	    else d:="0000";c:="0000";
	    end if;
	 elsif d<"1001" then d:=d+1;
	 else d:="0000";c:=c+1;
      end if;
   end if;
   oh<=c&d;
end process;
end Behavioral;