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fpga_dsp_portlink.fnsim.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
lcd.h
/***************************************************************************************
****************************************************************************************
* FILE : lcd.h
*
verilog.scr
/* link TOP design */
read COMPUTE_BLOCK.db
read CONVERTOR_CKT.db
read -format verilog TOP.v
current_design TOP
link
/* testability analysis */
set_test_hold 1 TEST_MODE
set_test_methodology full_sca
vhdl.scr
/* link TOP design */
read COMPUTE_BLOCK.db
read CONVERTOR_CKT.db
read -format vhdl TOP.vhd
current_design TOP
link
/* testability analysis */
set_test_hold 1 TEST_MODE
set_test_methodology full_scan
read.dc
###############################################################################
#
# Pre Synthesis Script
#
# This script only reads in the design and saves it in a DB file
#
# Author: Rudolf Uss
read_po.dc
###############################################################################
#
# Pre Synthesis Script
#
# This script only reads in the design and saves it in a DB file
#
# Author: Rudolf Usselmann
read_ao3.dc
###############################################################################
#
# Pre Synthesis Script
#
# This script only reads in the design and saves it in a DB file
#
# Author: Rudolf Usselmann
read_po3.dc
###############################################################################
#
# Pre Synthesis Script
#
# This script only reads in the design and saves it in a DB file
#
# Author: Rudolf Usselmann
read_ao.dc
###############################################################################
#
# Pre Synthesis Script
#
# This script only reads in the design and saves it in a DB file
#
# Author: Rudolf Usselmann