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Design 的代码
jvcustomd7d.dpk
package JvCustomD7D;
{
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DO NOT EDIT THIS FILE, IT IS GENERATED BY THE PACKAGE GENERATOR
ALWAYS EDIT TH
jvctrlsd7d.dpk
package JvCtrlsD7D;
{
-----------------------------------------------------------------------------
DO NOT EDIT THIS FILE, IT IS GENERATED BY THE PACKAGE GENERATOR
ALWAYS EDIT THE
jvdbd7d.dpk
package JvDBD7D;
{
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DO NOT EDIT THIS FILE, IT IS GENERATED BY THE PACKAGE GENERATOR
ALWAYS EDIT THE RE
top.mrp
Release 5.2i - Map F.28
Xilinx Mapping Report File for Design 'top'
Design Information
------------------
Command Line : map top.ngd
Target Device : 2v40
Target Package : cs144
Target Speed : -
top.mrp
Release 5.2i - Map F.28
Xilinx Mapping Report File for Design 'top'
Design Information
------------------
Command Line : map top.ngd
Target Device : 2v40
Target Package : cs144
Target Speed : -
top.mrp
Release 5.2i - Map F.28
Xilinx Mapping Report File for Design 'top'
Design Information
------------------
Command Line : map top.ngd
Target Device : 2v40
Target Package : cs144
Target Speed : -
xst_module_b.ptf
[module_b]
Implement Design=false
Synthesize=true
mod7cnt.ptf
[mode7cnt]
Design Entry Utilities=true
pll_waveforms.html
Sample Waveforms for pll.vhd
Sample behavioral waveforms for design file pll.vhd
The following waveforms show the behav
tmperr.err
WARNING:Cpld:828 - Signal 'rd_en.RSTF' has been minimized to 'GND'.
The signal is removed.
WARNING:Cpld:828 - Signal 'wr_en.RSTF' has been minimized to 'GND'.
The signal is removed.
ERROR:Cp