top.mrp

Xilinx ISE 官方源代码盘第八章

Release 5.2i - Map F.28
Xilinx Mapping Report File for Design 'top'

Design Information
------------------
Command Line   : map top.ngd 
Target Device  : 2v40
Target Package : cs144
Target Speed   : -5
Mapper Version : virtex2 -- $Revision: 1.4 $
Mapped Date    : Thu Mar 27 15:47:29 2003

Design Summary
--------------
Number of errors:      0
Number of warnings:    3
Logic Utilization:
  Number of Slice Flip Flops:          10 out of     512    1%
  Number of 4 input LUTs:               5 out of     512    1%
Logic Distribution:
    Number of occupied Slices:                           13 out of     256    5%
    Number of Slices containing only related logic:      13 out of      13  100%
    Number of Slices containing unrelated logic:          0 out of      13    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:              5 out of     512    1%

   Number of bonded IOBs:              15 out of      88   17%
   Number of GCLKs:                     4 out of      16   25%
   Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  7,125
Additional JTAG gate count for IOBs:  720
Peak Memory Usage:  53 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:MapLib:328 - Block instance_c is not a recognized logical block. The
   mapper will continue to process the design but there may be design problems
   if this block does not get trimmed.
WARNING:MapLib:328 - Block instance_b is not a recognized logical block. The
   mapper will continue to process the design but there may be design problems
   if this block does not get trimmed.
WARNING:MapLib:191 - port net moda_data has driver within module, can't add
   pseudo-driver for in ports

Section 3 - Informational
-------------------------
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "bufg_moda" (output signal=moda_clk),
   BUFGP symbol "bufg_modb" (output signal=modb_clk),
   BUFGP symbol "bufg_modc" (output signal=modc_clk),
   BUFG symbol "globalclk" (output signal=clk_top)
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.

Section 4 - Removed Logic Summary
---------------------------------

Section 5 - Removed Logic
-------------------------

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| dll_rst                            | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| ipad_dll_clk_in                    | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| mod_c_out                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| moda_clk_pad                       | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| moda_data                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| moda_out                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| modb_clk_pad                       | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| modb_data                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| modb_out                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| modc_clk_pad                       | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| modc_data                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| modc_out                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| obuft_out                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| top2a_c                            | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| top2b                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
AREA_GROUP AG_instance_a
  RANGE: SLICE_X2Y15:SLICE_X3Y2
  RANGE: RAMB16_X1Y1:RAMB16_X0Y1
  No COMPRESSION specified for AREA_GROUP AG_instance_a
  AREA_GROUP Logic Utilization:
  Number of Slice Flip Flops:     8 out of     56   14%
  Logic Distribution:
    Number of occupied Slices:                           8 out of     28   28%
    Number of Slices containing only related logic:      8 out of      8  100%
  Total Number 4 input LUTs:      2 out of     56    3%
      Number used as logic:                     2


Section 10 - Modular Design Summary
-----------------------------------
The following logic was added to the design to satisfy the
active module's interface.  These interface components will
be removed during the Modular Design Final Assembly Phase.

  2 Flip Flops.
  2 LUTs
  0 TBUFs

To get a listing of the active module port nets, set the
"XIL_MAP_LISTPORTNETS" environment variable and rerun map.