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console.log
# Design Explorer: Shortcut to "D:\My_Designs\Samples_63\Generator\generator.aws" design added.
readme
This directory contains Synopsys Design Compiler synthesis script.
top.scr - main synthesis script
read_design.inc - used by top.scr to read design files
run_syn - shell script to invoke design c
text1.c
#include
#include
void main(coid)
{
//const unsigned design[10]={0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90,0xC0};
const unsigned design[10]={1,2,3,4,5,6,7,8,9,0};
co
http:^^dis.cs.umass.edu^research^dtt.html
Date: Wednesday, 15-Jan-97 02:08:39 GMT
Server: NCSA/1.3
MIME-version: 1.0
Content-type: text/html
Last-modified: Wednesday, 22-Mar-95 16:48:03 GMT
Content-length: 4784
Design-to-time Real-tim
decoder24.bld
Release 8.2i ngdbuild I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\bin\nt\ngdbuild.exe -ise
D:/MY_DESIGN/ISE/LXJ/decoder24/decoder24.ise -intstyle ise -dd
nco_v7_1_add.tcl
set_global_assignment -name "VERILOG_FILE" "D:/eda_design/altera_design/dspbuilder_design/NCO_ip/DSPBuilder_nco_ip_design_import/nco_v7_1_st.v";
set_global_assignment -name "VHDL_FILE" "D:/eda_design
modulator_translate.nlf
Release 8.1.03i - netgen I.27
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Command Line: netgen -intstyle ise -w -dir netgen/translate -ofmt verilog -sim
modulator.ngd modulator_transl
dc.tcl
source -echo -verbose dc_setup.tcl
#################################################################################
# Design Compiler Reference Methodology Script for Top-Down Flow &
# Design Compil
dc_mv.tcl
source -echo -verbose dc_setup.tcl
#################################################################################
# Design Compiler Multi-Voltage UPF Reference Methodology Script for Top-Down Flow