modulator_translate.nlf

运用FPGA控制AD9957的操作

Release 8.1.03i - netgen I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -w -dir netgen/translate -ofmt verilog -sim
modulator.ngd modulator_translate.v  

Reading design 'modulator.ngd' ...
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing Verilog netlist file
'E:\work\modulator_single\netgen\translate\modulator_translate.v' ...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM simulation library for
   correct compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 57576 kilobytes