代码搜索：Data Science

找到约 10,000 项符合「Data Science」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/359289/10156760

mdb data.mdb

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www.eeworm.com/read/359174/10162752

stx data.stx

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www.eeworm.com/read/359174/10162813

ngr data.ngr

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www.eeworm.com/read/359174/10162861

sym data.sym

VERSION 5 BEGIN SYMBOL data SYMBOLTYPE BLOCK TIMESTAMP 2008 1 10 10 14 50 SYMATTR VeriModel "data" SYMPIN 0 -96 Input sclk SYMPIN 384 -96 Output sdata BEGIN DISPLAY 192 -136 ATTR SymbolName
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www.eeworm.com/read/359174/10162881

lso data.lso

work
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www.eeworm.com/read/359174/10162917

bin data.bin

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www.eeworm.com/read/359174/10162924

spl data.spl

[Inputs] sclk [Outputs] sdata [BiDir] [ATTRIBUTES] VeriModel data
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www.eeworm.com/read/359174/10163011

syr data.syr

Release 7.1.04i - xst H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 1.89 s | Elapsed : 0.00 / 2.00 s --> Parameter xsthdpdir set
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www.eeworm.com/read/359174/10163077

xst data.xst

set -tmpdir __projnav set -xsthdpdir ./xst run -ifn data.prj -ifmt mixed -ofn data -ofmt NGC -p xc3s400-4-pq208 -top data -opt_mode Speed -opt_level 1 -iuc NO -lso data.lso -keep_hierarch
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www.eeworm.com/read/359174/10163222

v data.v

module data(sclk,sdata); input sclk; output sdata; reg sdata; reg [4:0]e,state6; reg [15:0]datain; initial begin sdata
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