data.syr

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.89 s | Elapsed : 0.00 / 2.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: data.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "data.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "data"
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : data
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : data.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "data.v"
Module <data> compiled
No errors in compilation
Analysis of file <"data.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <data>.
WARNING:Xst:854 - "data.v" line 8: Ignored initial statement.
Module <data> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <data>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <data>.
    Related source file is "data.v".
    Using one-hot encoding for signal <state6>.
    Found 1-bit register for signal <sdata>.
    Found 5-bit adder for signal <$n0008> created at line 18.
    Found 16-bit register for signal <data>.
    Found 5-bit register for signal <e>.
    Found 3-bit register for signal <state6>.
    Summary:
	inferred  25 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <data> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 5-bit adder                       : 1
# Registers                        : 4
 1-bit register                    : 1
 16-bit register                   : 1
 3-bit register                    : 1
 5-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <data_0> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_1> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_2> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <state6_0> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1710 - FF/Latch  <data_13> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_12> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_15> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sdata> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_14> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <state6_1> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_3> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_4> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_5> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_6> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_7> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_8> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_9> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_10> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_11> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1291 - FF/Latch <e_4> is unconnected in block <data>.
WARNING:Xst:1291 - FF/Latch <e_3> is unconnected in block <data>.
WARNING:Xst:1291 - FF/Latch <state6_2> is unconnected in block <data>.
WARNING:Xst:1291 - FF/Latch <e_0> is unconnected in block <data>.
WARNING:Xst:1291 - FF/Latch <e_2> is unconnected in block <data>.
WARNING:Xst:1291 - FF/Latch <e_1> is unconnected in block <data>.

Optimizing unit <data> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block data, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : data.ngr
Top Level Output File Name         : data
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 2

Macro Statistics :
# Registers                        : 4
#      1-bit register              : 1
#      16-bit register             : 1
#      3-bit register              : 1
#      5-bit register              : 1

Cell Usage :
# BELS                             : 1
#      GND                         : 1
# IO Buffers                       : 1
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of bonded IOBs:                  2  out of    141     1%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
CPU : 6.38 / 8.44 s | Elapsed : 6.00 / 8.00 s
 
--> 

Total memory usage is 101656 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   26 (   0 filtered)
Number of infos    :    1 (   0 filtered)