代码搜索：DSPbuilder
找到约 118 项符合「DSPbuilder」的源代码
代码结果 118
www.eeworm.com/read/226889/14449339
txt readme.txt
//Write by Alex.liu
1.覆盖\DSPBuilder\Altlib下的signalcompiler.exe
2. 添加 license.dat 里面的DSPlicense的
FEATURE C4D5_512A alterad 9999.12 07-aug-2006 uncounted 62A1E82639EE \
VENDOR_STRING=9f6cj2mzaEUV
www.eeworm.com/read/235773/14053443
txt 读我.txt
#用DSP-Builder_6.1破解器.exe破解C:\altera\61\DSPBuilder\Altlib\下的signalcompiler.exe文件（运行DSP-Builder_6.1破解器.exe后,首先要点击“浏览”选中signalcompiler.exe，安装默认的signalcompiler.exe路径是在C:\altera\61\DSPBuilder\Altlib\下，选中si
www.eeworm.com/read/305828/13760102
bat sinoutqt.bat
cd "D:\simulink"
"C:\altera\quartus60\bin\quartus_cmd" -f "D:\simulink\Sinout_quartus.tcl" > "D:\simulink\DSPBuilder_Sinout\Sinoutqt.txt"
www.eeworm.com/read/233765/14137179
rpt nco_ip_design.flow.rpt
Flow report for nco_ip_design
Wed Jun 06 12:01:14 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Lega
www.eeworm.com/read/222378/14693874
bat ddsqt.bat
cd "d:\matlab6\work\gw48_sopc_1c6_demo\dds_l"
"E:\EDA\bin\quartus_cmd" -f "d:\matlab6\work\gw48_sopc_1c6_demo\dds_l\dds_quartus.tcl" > "d:\matlab6\work\gw48_sopc_1c6_demo\dds_l\DSPBuilder_dds\ddsqt.t
www.eeworm.com/read/186842/8902180
bat ask_modenqt_fit.bat
cd "E:\sunyu\PGC\dspbuild\200651000756-99\ASK"
"D:\altera\quartus60\bin\quartus_sh" -t "E:\sunyu\PGC\dspbuild\200651000756-99\ASK\ask_moden_quartus.tcl" 2
"D:\altera\quartus60\bin\quartus_sh" -t
www.eeworm.com/read/395400/8180243
bat singtqt_map.bat
cd "e:\ljltx\sinout"
"D:\altera\Quartus II 6\bin\quartus_sh" -t "e:\ljltx\sinout\singt_quartus.tcl" 1
"D:\altera\Quartus II 6\bin\quartus_sh" -t "D:\altera\DSPBuilder\AltLib\get_report_quartus_m
www.eeworm.com/read/186842/8902339
hif ask_moden.hif
Version 6.0 Build 178 04/27/2006 SJ Full Version
39
2097
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
d
www.eeworm.com/read/233765/14137201
vhd nco_ip_design_gn8343.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity nco_ip_design_GN8343 is
port(
Clock : in STD_LOGIC;
aclr : in STD_LOGIC);
e
www.eeworm.com/read/359802/10124385
bat dds_topqt_map.bat
cd "D:\my_eda3\DDS"
"e:\altera\70\quartus\bin\quartus_sh" -t "D:\my_eda3\DDS\dds_top_quartus.tcl" 1
"e:\altera\70\quartus\bin\quartus_map" dds_top --generate_symbol="dds_top.vhd"
"e:\altera\70\q