nco_ip_design_gn8343.vhd

来自「NCO的VHDL程序」· VHDL 代码 · 共 30 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity nco_ip_design_GN8343 is  
	port(
		Clock : in STD_LOGIC;
		aclr : in STD_LOGIC); 
end entity;
architecture rtl of nco_ip_design_GN8343 is
component alt_dspbuilder_clock_GN7862
	 generic (
			RESET : string := "ACTIVE_LOW";
			DOMAIN : string := "default"); 
	port(
		clock_out : out STD_LOGIC;
		aclr_out : out STD_LOGIC;
		clock : in STD_LOGIC;
		aclr_n : in STD_LOGIC); 
end component;
Begin
	Clock_0 : 
		component alt_dspbuilder_clock_GN7862
			port map(
				clock_out => open,
				aclr_out => open,
				clock => Clock,
				aclr_n => aclr);
end architecture;