代码搜索：DPLL
找到约 321 项符合「DPLL」的源代码
代码结果 321
www.eeworm.com/read/324454/13262506
v dpll.v
module DPLL(fin,fout,kclock,reset,k,N,H);
input fin,kclock,reset;
input[3:0] k;
input[7:0] N;
input[7:0] H;
output fout;
wire se,carry,borrow,idclock,idout,fout2;
DPLL_xor DPLL1(fin,fout,se);
DP
www.eeworm.com/read/316399/13523644
v dpll.v
module dpll(//input
clk,fin,reset,K,
//output
fout,fc2);
input clk,fin,reset;
input[3:0] K;
output fout,fc2;
wire fout,fc2;
wire hidclock,carryinc,borrowdec,
www.eeworm.com/read/312182/13616770
vhd dpll.vhd
library ieee;
use ieee.std_logic_1164.all;
entity dpll is
port (clk_original: in std_logic;
reset: in std_logic;
data: in std_logic;
clk_extracted: out std_logic
www.eeworm.com/read/481426/6640660
v dpll.v
// 该模块为数字锁相环
module dpll(
clk , //clock
rzcd , //code input double edge detection
bsyn ); //locked clock
input clk ;
input rzcd ;
output bsyn ;
reg bps ;
reg bsyn ;
reg [1:
www.eeworm.com/read/481426/6640728
sym dpll.sym
www.eeworm.com/read/259639/11776384
m dpll.m
clear all;
%close all;
%定义锁相环的工作模式：单载波为“1”、BPSK调制为“2”、QPSK调制为“3”
PLL_Mode = 1;
%仿真数据长度
Simulation_Length=10000;
%基带信号
if PLL_Mode == 1
I_Data=ones(Simulation_Length,1);
Q_Data=I_Data;
else i
www.eeworm.com/read/339072/12262353
inc dpll.inc
--Copyright (C) 1991-2005 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any outpu
www.eeworm.com/read/339072/12262456
vhd dpll.vhd
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: DPLL.vhd
-- Megafunc
www.eeworm.com/read/339072/12263809
bsf dpll.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/232417/14195524
txt dpll.txt
library ieee;
use ieee.std_logic_1164.all;
entity yxor is
port (x1,x2: in std_logic;
y:out std_logic);
end entity yxor;
architecture art1 of yxor is
begin
y