dpll.txt

数字锁相环的源代码。用硬件编程语言VHDL编写。

library ieee;
use ieee.std_logic_1164.all;

entity yxor is
port (x1,x2: in std_logic;
y:out std_logic);
end entity yxor;

architecture art1 of yxor is 
begin
y<=x1 xor x2;
end architecture art1; 


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity id_controller is
port (inc,dec,clk: in std_logic; 
out1:out std_logic);
end entity id_controller;

architecture art4 of id_controller is 
signal tmp  :std_logic_vector(1 downto 0);
signal cont :std_logic_vector(1 downto 0);
signal tmp1:std_logic;
begin
process(clk,inc,dec)
begin
if (clk'event and clk='1') then
   if inc='1' then
      cont<="01";       
   elsif dec='1' then
      cont<="11";
   else 
      cont<="10";
   end if;
end if;
end process;
process(clk,cont)
begin
if clk'event and clk='1' then
    if tmp<cont then
      tmp<=tmp+1;
    else
      tmp<="00";
      tmp1<=not tmp1;
    end if;
end if;
end process;

out1<=tmp1;
end architecture art4;





library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity div is
port (clk: in std_logic;
      n:in std_logic_vector(7 downto 0);
      y:out std_logic);
end entity div;

architecture art3 of div is 
signal k:std_logic_vector(7 downto 0);
signal tmp:std_logic;
begin
process(clk,n) is
begin
if clk'event and clk='1'then
   if k<n then
      k<=k+'1';
   else 
      k<="00000000";
      tmp<=not tmp;
   end if; 
end if; 
end process;
y<=tmp;
end architecture art3; 


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count_k is
port (clk,updn,en,d,c,b,a: in std_logic; 
inc,dec:out std_logic);
end entity count_k;


architecture art2 of count_k is 
signal cq,k,mo:std_logic_vector(16 downto 0);
signal temp1,temp2:std_logic;
signal instruction:std_logic_vector(3 downto 0);
begin
instruction<=d&c&b&a;
with instruction select 
mo<="00000000000000111" when "0001",
    "00000000000001111" when "0010",
    "00000000000011111" when "0011",
    "00000000000111111" when "0100",
    "00000000001111111" when "0101",
    "00000000011111111" when "0110",
    "00000000111111111" when "0111",
    "00000001111111111" when "1000",
    "00000011111111111" when "1001",
    "00000111111111111" when "1010",
    "00001111111111111" when "1011",
    "00011111111111111" when "1100",
    "00111111111111111" when "1101",
    "01111111111111111" when "1110",
    "11111111111111111" when "1111",
    "00000000000000111" when others;
process(clk,en,updn,k,cq)
begin
if clk'event and clk='1' then
   k<=mo;
    if en='1' then 
         if updn='0' then
            if cq<k then 
              cq<=cq+1;
            else cq<=(others=>'0');
            end if;
         else
            if cq>0 then
               cq<=cq-1;
            else cq<=k;
            end if;
            end if; 
   else cq<=(others=>'0');
   end if; 
end if; 
end process;

process(en,updn,cq,k) is
begin
if en='1' then 
   if updn='0' then 
       if cq=k then temp1<='1';
       else temp1<='0';
       end if; 
       temp2<='0';
   else
       if cq="00000000000000000"then temp2<='1';
       else temp2<='0';
       end if; 
       temp1<='0';
    end if;
else temp1<='0';temp2<='0';
end if;
end process;
inc<=temp1;dec<=temp2;
end architecture art2;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity system is
port (clk1,clk2,fin,en,d,c,b,a: in std_logic;
      n:in std_logic_vector(7 downto 0);
     fout:inout std_logic);
end entity system;

architecture art5 of system is

component yxor is
port (x1,x2: in std_logic;
y:out std_logic);
end component yxor;

component id_controller is
port (inc,dec,clk: in std_logic; 
out1:out std_logic);
end component id_controller;

component count_k is
port (clk,updn,en,d,c,b,a: in std_logic; 
inc,dec:out std_logic);
end component count_k;

component div is
port (clk: in std_logic;
      n:in std_logic_vector(7 downto 0);
y:out std_logic);
end component div;
signal s1,s2,s3,s4,s5:std_logic;
begin
  u1:yxor port map(fin,fout,s2);
  u2:count_k port map(clk1,s2,en,d,c,b,a,s3,s4);
  u3:id_controller port map(s3,s4,clk2,s1);
  u4:div port map(s1,n,fout);
end architecture art5;