代码搜索：DPLL
找到约 321 项符合「DPLL」的源代码
代码结果 321
www.eeworm.com/read/191974/8413891
psp dpll.psp
www.eeworm.com/read/191974/8413902
sof dpll.sof
www.eeworm.com/read/382881/8992722
bmp dpll.bmp
www.eeworm.com/read/276511/10733098
v dpll.v
module DPLL(sys_clock,
reset,
enable,
Fin,
Fout,
Kmode
);
input sys_clock,
reset,
enable,
Fin;
input
www.eeworm.com/read/276511/10733200
mpf dpll.mpf
; Copyright 1991-2007 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION
www.eeworm.com/read/275446/10816532
mdl dpll.mdl
Model {
Name "dpll"
Version 6.6
MdlSubVersion 0
GraphicalInterface {
NumRootInports 0
NumRootOutports 0
ParameterArgumentNames ""
ComputedModelVersio
www.eeworm.com/read/469231/6979484
gdf dpll.gdf
www.eeworm.com/read/460845/7239449
txt dpll.txt
支持论坛发展帖出全数字锁相环的verilog源代码,仿真已通过
module dpll(reset,clk,signal_in,signal_out,syn);
parameter para_K=4;
parameter para_N=16;
input reset;
input clk;
input signal_in;
output signal_out;
output
www.eeworm.com/read/450211/7488458
vhd dpll.vhd
-------数字锁相环------
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dpll is
port (clk :in std_logic; --clock
rz
www.eeworm.com/read/450211/7488488
bsf dpll.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to