代码搜索：DPA
找到约 133 项符合「DPA」的源代码
代码结果 133
www.eeworm.com/read/409487/11321251
c tbldpasetting.c
/*
* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
* This program is free software; you can redistribute it and/or
*
www.eeworm.com/read/24053/934830
pdf dpa50 w dc-dc双输出转换器.pdf
www.eeworm.com/read/24053/934823
pdf dpa5 w反激式dc-dc转换器.pdf
www.eeworm.com/read/316708/13518403
vhd bitslip_ctrl.vhd
-- File name : bitslip_ctrl.vhd (THE DPA FOR A DATA CHANNAL)
--
-- Description : This module is the bitslip control module for the DPA design
--
--
-- Date - revisio
www.eeworm.com/read/279175/10457442
bgp-typecode
BGP-4[+] UPDATE Attribute TypeCode list
Value Attribute References
=========================================================================
1 ORIGIN [RFC 1771]
www.eeworm.com/read/448648/7528308
bgp-typecode
BGP-4[+] UPDATE Attribute TypeCode list
Value Attribute References
=========================================================================
1 ORIGIN [RFC 1771]
www.eeworm.com/read/145256/12741768
bgp-typecode
BGP-4[+] UPDATE Attribute TypeCode list
Value Attribute References
=========================================================================
1 ORIGIN [RFC 1771]
www.eeworm.com/read/347114/11692795
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_dpa_receiver is
generic(
channel_width : integer := 10;
use_enable1 : string := "false";
enable_dpa
www.eeworm.com/read/347114/11699261
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_dpa_receiver is
generic(
channel_width : integer := 10;
use_enable1 : string := "false";
enable_dpa
www.eeworm.com/read/13899/285695
dsp c2_2_3.dsp
.entry dpa;
dpa: AR=AX0+AY0;
SR0=AR, AR=AX1+AY1+C;
SR1=AR;
RTS;
.ENDMOD