bitslip_ctrl.vhd

该代码用于实现串行数据的位移

--  File name :       bitslip_ctrl.vhd (THE DPA FOR A DATA CHANNAL)
--
--  Description :     This module is the bitslip control  module for the DPA design
-- 
--                    
--  Date - revision : --/--/2006
--
--  Author :          WANWEI  HUANG
--
--  Contact : e-mail  [e-mail]
--            phone   + 086 0371 63532770 
--
--  Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are 
--              provided to you "as is". NDSC and its licensors make and you 
--              receive no warranties or conditions, express, implied, 
--              statutory or otherwise, and NDSC specifically disclaims any 
--              implied warranties of merchantability, non-infringement, or 
--              fitness for a particular purpose. NDSC does not warrant that 
--              the functions contained in these designs will meet your 
--              requirements, or that the operation of these designs will be 
--              uninterrupted or error free, or that defects in the Designs 
--              will be corrected. Furthermore, NDSC does not warrant or 
--              make any representations regarding use or the results of the 
--              use of the designs in terms of correctness, accuracy, 
--              reliability, or otherwise. 
--
--              LIMITATION OF LIABILITY. In no event will NDSC or its 
--              licensors be liable for any loss of data, lost profits, cost 
--              or procurement of substitute goods or services, or for any 
--              special, incidental, consequential, or indirect damages 
--              arising from the use or operation of the designs or 
--              accompanying documentation, however caused and on any theory 
--              of liability. This limitation will apply even if Xilinx 
--              has been advised of the possibility of such damage. This 
--              limitation shall apply not-withstanding the failure of the 
--              essential purpose of any limited remedies herein. 
--
--  Copyright ? 2006 NDSC
--  All rights reserved 
-- 
--*****************************************************************************
--------------------------------------------------- 该模块用于实现串行数据的位移（1位以上）---------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.Std_logic_arith.all;
use IEEE.Std_logic_unsigned.all;
use IEEE.numeric_std.all;
use IEEE.numeric_bit.all;
use work.all;

library UNISIM;
use UNISIM.vcomponents.all;


ENTITY bitslip_ctrl IS
   PORT (
      datain                  : IN std_logic_vector(7 DOWNTO 0);   
      rst                     : IN std_logic;   
      bitslip_en              : IN std_logic;   
      clkdiv                  : IN std_logic;   
      bitslip                 : OUT std_logic;   
      done                    : OUT std_logic
--    error                   : OUT std_logic
     );   
END ENTITY bitslip_ctrl;

ARCHITECTURE bitslip_ctrl_arch OF bitslip_ctrl IS


   SIGNAL Current_State            :  std_logic_vector(3 DOWNTO 0);   
   SIGNAL Next_State               :  std_logic_vector(3 DOWNTO 0);   
--   SIGNAL counter                  :  std_logic_vector(7 DOWNTO 0);   
--   SIGNAL cnt_rst                  :  std_logic;   
--   SIGNAL cnt_inc                  :  std_logic;   
   SIGNAL pattern_detect           :  std_logic;   
--   CONSTANT  BITSLIP_LIMIT         :  std_logic_vector(7 DOWNTO 0) := "00010100";    

   --Declare state machine parameters
   -- Bitslip Control State Machine
   CONSTANT  START                 :  std_logic_vector(3 DOWNTO 0) := "0000";    -- 0
   CONSTANT  START_WAIT1           :  std_logic_vector(3 DOWNTO 0) := "0001";    -- 1
   CONSTANT  START_WAIT2           :  std_logic_vector(3 DOWNTO 0) := "0010";    -- 2
   CONSTANT  CHECK_PATTERN         :  std_logic_vector(3 DOWNTO 0) := "0011";    -- 3
   CONSTANT  BITSLIP_ASSERT        :  std_logic_vector(3 DOWNTO 0) := "0100";    -- 4
   CONSTANT  WAIT_BITSLIP1         :  std_logic_vector(3 DOWNTO 0) := "0101";    -- 5
   CONSTANT  WAIT_BITSLIP2         :  std_logic_vector(3 DOWNTO 0) := "0110";    -- 6
   CONSTANT  WAIT_BITSLIP3         :  std_logic_vector(3 DOWNTO 0) := "0111";    -- 7
   CONSTANT  WAIT_BITSLIP4         :  std_logic_vector(3 DOWNTO 0) := "1000";    -- 8
   CONSTANT  BITSLIP_DONE          :  std_logic_vector(3 DOWNTO 0) := "1001";    -- 9
   CONSTANT  WAIT1_DONE            :  std_logic_vector(3 DOWNTO 0) := "1010";    -- 10
--   CONSTANT  ERROR_STATE           :  std_logic_vector(3 DOWNTO 0) := "1011";    -- 11
   SIGNAL bitslip_int              :  std_logic;   
   SIGNAL done_int                 :  std_logic;   
--   SIGNAL error_int                :  std_logic; 

   BEGIN
   bitslip <= bitslip_int;
   done <= done_int;
    
   -- Pattern Detect Logic   
   -- Detect a "00001111" pattern from ISERDES output
   pattern_detect <= ((((((NOT datain(7) AND NOT datain(6)) AND  NOT datain(5)) AND NOT datain(4)) AND  datain(3)) AND  datain(2)) AND  datain(1)) AND  datain(0) ;

   -- All-purpose  
   -- Current State Logic
   PROCESS (clkdiv, rst)
   BEGIN
      IF (rst = '1') THEN
         Current_State <= START;   
      ELSIF rising_edge(clkdiv) THEN
         Current_State <= Next_State;    
      END IF;
   END PROCESS;

   -- Output forming logic   
   PROCESS (Current_State)
   BEGIN
      CASE Current_State IS
         WHEN START =>
--                  cnt_rst <= '1';    
--                  cnt_inc <= '0';    
                  bitslip_int <= '0';    
                  done_int <= '0';    
--                  error_int <= '0';
			       
         -- Insert wait states after START to account for pipeline stages         
         -- in channel select MUX.         
         WHEN START_WAIT1 =>
--                  cnt_rst <= '0';    
--                  cnt_inc <= '0';    
                  bitslip_int <= '0';    
                  done_int <= '0';    
--                  error_int <= '0';    
         WHEN START_WAIT2 =>
--                  cnt_rst <= '0';    
--                  cnt_inc <= '0';    
                  bitslip_int <= '0';    
                  done_int <= '0';    
--                  error_int <= '0';    
         WHEN CHECK_PATTERN =>
--                  cnt_rst <= '0';    
--                  cnt_inc <= '0';    
                  bitslip_int <= '0';    
                  done_int <= '0';    
--                  error_int <= '0';    
         WHEN BITSLIP_ASSERT =>
--                  cnt_rst <= '0';    
--                  cnt_inc <= '1';    
                  bitslip_int <= '1';    
                  done_int <= '0';    
--                  error_int <= '0';    
         WHEN WAIT_BITSLIP1 =>
--                  cnt_rst <= '0';    
--                  cnt_inc <= '0';    
                  bitslip_int <= '0';    
                  done_int <= '0';    
--                  error_int <= '0';    
         WHEN WAIT_BITSLIP2 =>
--                  cnt_rst <= '0';    
--                  cnt_inc <= '0';    
                  bitslip_int <= '0';    
                  done_int <= '0';    
--                  error_int <= '0';    
         WHEN WAIT_BITSLIP3 =>
--                  cnt_rst <= '0';    
--                  cnt_inc <= '0';    
                  bitslip_int <= '0';    
                  done_int <= '0';    
 --                 error_int <= '0';    
         WHEN WAIT_BITSLIP4 =>
--                  cnt_rst <= '0';    
--                  cnt_inc <= '0';    
                  bitslip_int <= '0';    
                  done_int <= '0';    
--                  error_int <= '0';    

         -- Bitslip operation is complete. The training pattern has been detected. The data         
         -- channel has been word aligned.           
         WHEN BITSLIP_DONE =>
--                  cnt_rst <= '1';    
--                  cnt_inc <= '0';    
                  bitslip_int <= '0';    
                  done_int <= '1';    
--                 error_int <= '0';    
         WHEN WAIT1_DONE =>
--                  cnt_rst <= '1';    
--                  cnt_inc <= '0';    
                  bitslip_int <= '0';    
                  done_int <= '0';    
--                  error_int <= '0';    
--         WHEN ERROR_STATE =>
--                  cnt_rst <= '0';    
--                  cnt_inc <= '0';    
--                  bitslip_int <= '0';    
--                  done_int <= '0';    
--                  error_int <= '1';    
         WHEN OTHERS  =>
--                  cnt_rst <= '0';    
--                  cnt_inc <= '0';    
                  bitslip_int <= '0';    
                  done_int <= '0';    
--                  error_int <= '0';             
      END CASE;
   END PROCESS;
                 	
   PROCESS (Current_State, rst, bitslip_en,  pattern_detect)
   BEGIN
      CASE Current_State IS
          WHEN START =>
               IF (rst = '1') THEN
                   Next_State <= START;    
               ELSIF (bitslip_en = '0') THEN
                   Next_State <= START;    
               ELSE
                   Next_State <= START_WAIT1;    
               END IF;                                                  
         -- Insert wait states after START to account for pipeline stages         
         -- in channel select MUX.         
           WHEN START_WAIT1 =>
                  Next_State <= START_WAIT2;    
           WHEN START_WAIT2 =>
                  Next_State <= CHECK_PATTERN;    
           WHEN CHECK_PATTERN =>
                  IF (pattern_detect = '1') THEN
                     -- If Paterrn = 00001111                     
                     Next_State <= BITSLIP_DONE;    
                  ELSE
                     Next_State <= BITSLIP_ASSERT;    
                  END IF;
         -- Activate one bitslip operation         
           WHEN BITSLIP_ASSERT =>
                  Next_State <= WAIT_BITSLIP1;    
           WHEN WAIT_BITSLIP1 =>
                  Next_State <= WAIT_BITSLIP2;    
           WHEN WAIT_BITSLIP2 =>
                  Next_State <= WAIT_BITSLIP3;    
           WHEN WAIT_BITSLIP3 =>
                  Next_State <= WAIT_BITSLIP4;    
           WHEN WAIT_BITSLIP4 =>
                  Next_State <= CHECK_PATTERN;  
			     
         -- Bitslip operation is complete. The training pattern has been detected. The data         
         -- channel has been word aligned.           
           WHEN BITSLIP_DONE =>
                  Next_State <= WAIT1_DONE;    
           WHEN WAIT1_DONE =>
                  Next_State <= START;    
--           WHEN ERROR_STATE =>
--                  Next_State <= ERROR_STATE;    
           WHEN OTHERS  =>
                  Next_State <= START;             
       END CASE;
   END PROCESS;

END ARCHITECTURE bitslip_ctrl_arch;