代码搜索：Controller
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www.eeworm.com/read/214738/15090417
vhd controller.vhd
--
-- File: controller.vhd
-- 控制模块：输入clk1为1HZ时钟信号,reset,输出为LED信号和倒计时值
library IEEE;
use IEEE.std_logic_1164.all;
entity controller is
port (
clk1: in STD_LOGIC;
reset: in STD_LOGIC;
www.eeworm.com/read/214724/15090870
h controller.h
// controller.h
//
// Copyright (c) 2000 Symbian Ltd. All rights reserved.
//
#ifndef __CONTROLLER_H
#define __CONTROLLER_H
#include
#include
#include
www.eeworm.com/read/214724/15090875
cpp controller.cpp
// controller.cpp
//
// Copyright (c) 2000 Symbian Ltd. All rights reserved.
//
#include "controller.h"
#include "appview.h"
#include
#include
#include
www.eeworm.com/read/213968/15119156
v controller.v
module controller(clk1,clk2,n,OE); //全加器模块
input clk1,clk2; //定义clk1、clk2
output [3:0] n; //定义输出的控制信号n
output OE; //定义输出的控制信号OE
reg [3:0] n,nextn; //定义寄存器型状态转换变量变量
reg OE;
wire p;
reg t,m;
www.eeworm.com/read/213195/15141099
h controller.h
#ifndef _RTW_HEADER_Controller_h_
#define _RTW_HEADER_Controller_h_
#ifndef _Controller_COMMON_INCLUDES_
# define _Controller_COMMON_INCLUDES_
#include
#include
#include
www.eeworm.com/read/213195/15141100
c controller.c
#include "Controller.h"
#include "Controller_private.h"
D_Work_Controller Controller_DWork;
ExternalInputs_Controller Controller_U;
ExternalOutputs_Controller Controller_Y;
void Controlle
www.eeworm.com/read/211218/15184632
vhd controller.vhd
--******************************************************************************
--
-- Xilinx, Inc. 2002 www.xilinx.com
--
-- XAPP 253 - Synthesizable DDR SDRAM Controller
--
-
www.eeworm.com/read/209015/15229129
class controller.class
www.eeworm.com/read/209015/15229167
class controller.class
www.eeworm.com/read/209015/15229188
java controller.java
import javax.microedition.midlet.MIDlet;
import javax.microedition.lcdui.Display;
public class Controller implements LogoListener, ListListener, GameListener{
public Controller( MIDlet app ){