controller.v

来自「Verilog 编写的fir滤波器」· Verilog 代码 · 共 33 行

module controller(clk1,clk2,n,OE);  //全加器模块
input clk1,clk2;  //定义clk1、clk2
output [3:0] n; //定义输出的控制信号n
output OE;     //定义输出的控制信号OE
reg [3:0] n,nextn;  //定义寄存器型状态转换变量变量
reg OE;
wire p;
reg t,m;       //定义中间变量   
assign p=!t&clk1;     //通过clk2采样clk1，当上一周期采到低电平且下一周期采到高电平即上升延时，将控制信号n置零
always@(posedge clk2)
   begin
     t=clk1;
     if(p) n=0;
     else n=nextn;
   end
always@(n)         //当clk2来时，通过改变nextn的状态来改变n的状态，从而进行控制
  begin
       case(n)
           0:   begin  OE=1; nextn=1; end
           1:   begin  OE=0; nextn=2; end
           2:   begin  OE=0; nextn=3; end
           3:   begin  OE=0; nextn=4; end
           4:   begin  OE=0; nextn=5; end
           5:   begin  OE=0; nextn=6; end
           6:   begin  OE=0; nextn=7; end
           7:   begin  OE=0; nextn=8; end
           8:   begin  OE=0; nextn=9; end
           9:   begin  OE=0; nextn=0; end
           default: begin  OE=0; nextn=0; end
       endcase
   end
endmodule