代码搜索结果
找到约 10,000 项符合
Control System 的代码
control.h
#ifndef __CONTROL_H__
#define __CONTROL_H__
#include "..\ucos-ii\includes.h" /* uC/OS interface */
#include "..\inc\drv\figure.h"
#include "..\inc\drv\display.h"
#include "..\ucos
control.h
#pragma warning( disable: 4049 ) /* more than 64k source lines */
/* this ALWAYS GENERATED file contains the definitions for the interfaces */
/* File created by MIDL compiler version 6.00
control.vhd
--
--
-- control module (simulates SPIM control module)
--
--
library Synopsys, IEEE;
use Synopsys.attributes.all;
use IEEE.STD_LOGIC_1164.all;
entity control is
port( signal Op : i
control.vhd
---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
control.v
module control (addrin,countin,datein,clk,dateout,addrout);
input [2:0] addrin;
input [2:0] countin;
input clk,datein;
output dateout;
output [2:0] addrout;
assign dateout=(!clk)? da
control.java
package SimFrameWork;
public abstract class Control extends Thread{
public Control(){
}
public void run(){
active=true;
while(active){
update();
}
}
public void s
control.acf
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port
(
clk :in std_logic;
reset:in std_logic;
keydata :in std_logic_vector (3 downto 0);-- "1