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Control System 的代码
control.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CONTROL IS
PORT(OV:IN STD_LOGIC;
SELA,SELB:OUT STD_LOGIC;
S2,S3:OUT STD_LOGIC);
END CONTROL;
ARCHITECTURE ONE OF CONTROL IS
SIGNAL
control.rpt
Project Information d:\kechengshejitest\control.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 06/22/2007 01:59:21
Copyright (C) 1988-2000 Alt
control.hex
:020000040000FA
:39000000FFFF62FF3600FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF65
:39003900000C8001300006C00018000360000C80013000060000000
control.hif
HIF003
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, an
control.pin
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
control.java
//: Control.java
//package g3ds.joop.ch3;
import java.io.*;
/**
* A demo for statements
* @version 1.00, 10/01/03
* @author Global 3D Studio
* @see Kid
* @since Java OOP Ver.1
control.v
module control(std_f_sel,reset,clk,clear,cntover,cntlow);
output[1:0] std_f_sel;
output reset;
input clk,clear,cntover,cntlow;
reg[1:0] std_f_sel;
reg reset;
reg[5:0] present,next;
parameter st