control.vhd

来自「基于FLEX10K的频率计设计」· VHDL 代码 · 共 41 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY CONTROL IS
	PORT(OV:IN STD_LOGIC;
		 SELA,SELB:OUT STD_LOGIC;
		 S2,S3:OUT STD_LOGIC);
END CONTROL;

ARCHITECTURE ONE OF CONTROL IS
SIGNAL SSEL:STD_LOGIC_VECTOR(1 DOWNTO 0);

BEGIN
 	PROCESS(OV)
	BEGIN
		IF OV='1'THEN
		CASE (SSEL) IS
		WHEN"00"=>SSEL<="01";
				--S1<='0';
				S2<='1';
				S3<='0';
		WHEN"01"=>SSEL<="10";
				--S1<='0';
				S2<='0';
				S3<='1';
		WHEN"10"=>SSEL<="11";
				--S1<='1';
				S2<='1';
				S3<='1';
		WHEN OTHERS=>SSEL<="11";
				--S1<='1';
				S2<='1';
				S3<='1';
		END CASE;
		ELSE NULL;
	END IF;
	END PROCESS;
	SELA<=SSEL(0);SELB<=SSEL(1);
END ONE;