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Control 的代码
control.s
;***************************************************************************
; Copyright (C) Hynix Semiconductor Limited 2002. All rights reserved.
;***********************************************
control.v
module control(std_f_sel,reset,clk,clear,cntover,cntlow);
output[1:0] std_f_sel;
output reset;
input clk,clear,cntover,cntlow;
reg[1:0] std_f_sel;
reg reset;
reg[5:0] present,next;
parameter st
control.v
module control(clk1,clk2,i,OE,reset);
parameter state_reset=9;
parameter state_spare=8;
input clk1,clk2;
output[2:0] i;
output OE;
output reset;
reg reset;
reg OE;
reg[2:0] i;
reg[3:0] state,next_stat
control.c
/****************************************************************
* ARMSYS7 S3C44B0X developer's notes *
****************************************************************
1. 2005.5.17::
control.h
#ifndef __CONTROL_H__
#define __CONTROL_H__
#include "..\ucos-ii\includes.h" /* uC/OS interface */
#include "..\inc\drv\figure.h"
#include "..\ucos-ii\add\list.h"
#define OSCtrlMemSize
control.v
`timescale 1ns/10ps
module control(//input
nrst,clk,
exe_program,mem_dout,
rega2ctl,regb2ctl,
//output
ctl_wen,
ctl_din,ctl_addr,
rega_sel,regb_sel,regc_sel,
data2reg,cur
control.vhd
--core_design
--control
--all right reserved
library ieee;
use ieee.std_logic_1164.all;
entity control is
port (reset:in std_logic;
op : in std_logic_vector (5 downto 0); -- T