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control(60).cnf

control.tcl

project add_assignment "" "control" "" "" "EDA_DESIGN_ENTRY_SYNTHESIS_TOOL" "SYNPLIFY" project add_assignment "" "eda_design_synthesis" "" "" EDA_INPUT_DATA_FORMAT EDIF project add_assignment "" "ed

control(11).cnf

control(67).cnf

control(13).cnf

control(54).cnf

control(24).cnf

control(35).cnf

control.ndb

control.tlg

Synthesizing work.control.body_control Post processing for work.control.body_control @W:"H:\can\cpld\rev_1\control.vhd":367:4:367:5|Optimizing register bit wr_a_up(0) to a constant 0 @W:"H:\can\cpl