control.tlg

一个关于4CAN卡的硬件程序,用VHDL编写.就是4路CAN总线

Synthesizing work.control.body_control
Post processing for work.control.body_control
@W:"H:\can\cpld\rev_1\control.vhd":367:4:367:5|Optimizing register bit wr_a_up(0) to a constant 0
@W:"H:\can\cpld\rev_1\control.vhd":425:4:425:5|Optimizing register bit wr_a_down(0) to a constant 0
@W:"H:\can\cpld\rev_1\control.vhd":492:4:492:5|Optimizing register bit wr_b_up(0) to a constant 0
@W:"H:\can\cpld\rev_1\control.vhd":548:4:548:5|Optimizing register bit wr_b_down(0) to a constant 0
@W:"H:\can\cpld\rev_1\control.vhd":356:2:356:3|Input highz to this expression [tri] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W:"H:\can\cpld\rev_1\control.vhd":481:2:481:3|Input highz to this expression [tri] has undriven bits which are being tied to 0 - a simulation mismatch is possible