代码搜索：Control
找到约 10,000 项符合「Control」的源代码
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www.eeworm.com/read/171126/9769651
vhd fupin_control.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fupin_control is
Port ( clk2,sw1_2,sw2_2 ,s
www.eeworm.com/read/270171/11046165
ico control-panel.ico
www.eeworm.com/read/270171/11046208
png control-panel.png
www.eeworm.com/read/415978/11046336
v control_interface.v
/******************************************************************************
*
* LOGIC CORE: Control Interface - Top level module
* MODULE NAME: control_interface()
* COM
www.eeworm.com/read/269852/11073139
tdf pll_control.tdf
--//////////////////////////////////////////////////////////////////////////////////////////////////////////// // 该电路为外部锁相环的控制电路；
www.eeworm.com/read/415054/11085000
java workflow_control.java
package treedoc;
// 功能
// WORKFLOW客户处理层和底层的接口,功能是调用workflow_engine获得流程访问序列
// 通知服务器调用活动节点对应的USERID开始处理预先定义的活动,并将需要处理的数
// 据提交给客户处理界面
// 一旦客户处理完成,返回该类,则重新激活workflow_engine,进行下一个节点的处理流程
// 该类主 ...
www.eeworm.com/read/268502/11136425
qpf vga_control.qpf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/268502/11136440
bdf vga_control.bdf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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bsf vga_control.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/413870/11138779
c rate_control.c
#include "global_declare.h"
//#include "encodemain.h"
#include "def_gary.h"
const int max_quant_IVOP = 12;
const int min_quant_IVOP = 2;
const int max_quant_PVOP = 12;
const int min_quant_PVOP