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Control 的代码
control.v
module control(std_f_sel,reset,clk,clear,cntover,cntlow);
output[1:0] std_f_sel;
output reset;
input clk,clear,cntover,cntlow;
reg[1:0] std_f_sel;
reg reset;
reg[5:0] present,next;
parameter st
control.v
module cntrol(
reset,rst,clk16x,tsre,tbre,din,dout,rdn,wrn,led,data_ready
);
input reset;
input clk16x;
input tsre;
input tbre;
input data_ready;
output rst;
control.h
#ifndef __CONTROL_H__
#define __CONTROL_H__
#include "..\ucos-ii\includes.h" /* uC/OS interface */
#include "..\inc\drv\figure.h"
#include "..\inc\drv\display.h"
#include "..\ucos
control.h
#pragma warning( disable: 4049 ) /* more than 64k source lines */
/* this ALWAYS GENERATED file contains the definitions for the interfaces */
/* File created by MIDL compiler version 6.00
control.aspx
Untitled Document
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity control is
port(
clk: in std_logic;
reset: in std
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity control is
port(
clk: in std_logic;
reset: in std
control.v
module control(EN_in,SW1,RST,Red1,Red2,Yellow1,Yellow2,Green1,Green2);
output Red1;
output Red2;
output Yellow1;
output Yellow2;
output Green1;
output Green2;
input [1:0] EN_in;
input
control.v
/*乘法控制版,注意相应数据通路中要把clock导入。 无ldr，str push，pop,*/
module control(op2,op3,op4,op5,Rz3,Rz4,Rx2,Ry2,pc_in,IR2_in,mp1_sel,mp2_sel,mp3_pre_sel,mp3_sel,
aluop,IR3_in,x3_in,y3_in,rw,z4_in,mp4_sel,Rz_in,
Rz
control.c
#include
#include
#include
#include
sbit CS=P3^7;
sbit ALE=P3^5;
sbit RD=P3^0;
sbit WR=P3^1;
#define uchar unsigned char
#define uint unsigned int