control.vhd

此程序为脉宽测量电路vhdl代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity control is
port(
	clk: in std_logic;
	reset: in std_logic;
	pulse: in std_logic;
	s_state: out std_logic_vector (1 downto 0)
	);
end control;

architecture behaver of control is
	type mystate is (s0,s1,s2);
	signal current_state, next_state: mystate;
begin
	process (clk,reset)
	begin
		if clk'event and clk='1' then
			case current_state is
				when s0 => next_state<=s1;
				when s1 => next_state<=s2;
				when s2 => next_state<=s0;
			end case;
		end if;
	end process;
	
	process (clk,reset,pulse)
	begin
		if reset='0' then
			current_state<=s0;
		elsif clk'event and clk='1' then
			case current_state is
				when s0 =>
					s_state<="00";
					if pulse='0' then
						current_state<=next_state;
					end if;					
				when s1 =>
					s_state<="01";
					if pulse='1' then
						current_state<=next_state;
					end if;
				when s2 =>
					s_state<="11";
			end case;
		end if;
	end process;
end  behaver;