代码搜索：Concurrent
找到约 2,002 项符合「Concurrent」的源代码
代码结果 2,002
www.eeworm.com/read/406100/11449378
vhd majority_voter.vhd
--majority_voter.vhd
--DOWNLOAD FROM WWW.HUSOON.COM
--***************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--***************************************
ENTITY majo
www.eeworm.com/read/113597/15452497
flt sample1.flt
# SAMPLE1.FLT
# Sample filtering file number 1, using only title includes/excludes.
# Extract MS-DOS calls, but exclude DR-DOS-specific, DOS-extender, and
# non-DOS networking calls.
# Note: a few
www.eeworm.com/read/420682/10781226
cmd _impact.cmd
setpreference -novice
setpreference -concurrent_mode
setpreference -stop_on_failure
setPreference -fixClock
setPreference -PC4_5M
setMode -bs
setMode -bs
setMode -bs
setCable -port auto
setMo
www.eeworm.com/read/131315/5935803
sh mc6000.sh
# defaults for the masscomp (concurrent) 6000 series running RTU 5.0
cppstdin=/lib/cpp
cmd_cflags='optimize=""'
tcmd_cflags='optimize=""'
d_mymalloc=define
www.eeworm.com/read/261270/11656446
v feedkmodule.v
module FeedData
(
CLK,
Gain,
FeedK,
__output_name,
__output_name,
__inout_name,
__inout_name
);
input __input_name,
input __input_name,
output __output_name,
output
www.eeworm.com/read/142670/12931191
srr counter10.srr
#Program: Synplify Pro 8.1
#OS: Windows_NT
$ Start of Compile
#Tue Nov 01 21:02:40 2005
Synplicity VHDL Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplic
www.eeworm.com/read/142670/12931197
srr tb_counter10.srr
#Program: Synplify Pro 8.1
#OS: Windows_NT
$ Start of Compile
#Tue Nov 01 20:52:34 2005
Synplicity VHDL Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplic
www.eeworm.com/read/127694/6002612
makefile
include ../Make.defines
PROGS = serv01
all: ${PROGS}
# serv01: one fork per client (traditional concurrent server).
serv01: serv01.o web_child.o sig_chld_waitpid.o
${CC} ${CFLAGS} -o $@ serv01.o
www.eeworm.com/read/407963/11406986
vhd oeconbus.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
arch
www.eeworm.com/read/407958/11407033
vhd gatescon.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_