majority_voter.vhd

vhdl简单的例子程序

--majority_voter.vhd
--DOWNLOAD FROM WWW.HUSOON.COM

--***************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--***************************************

ENTITY majority_voter IS
	
	PORT(SW: IN std_logic_vector(3 DOWNTO 1);
		 L: OUT std_logic_vector(4 DOWNTO 3));
		 --L3 is a GREEN LED AND L4 is a RED LED
END majority_voter;

--****************************************

ARCHITECTURE concurrent OF majority_voter IS
BEGIN 
	WITH SW SELECT
	L <= 	  "01" WHEN "011",
			  "01" WHEN "101",
			  "01" WHEN "110",
			  "01" WHEN "111",
			  "10" WHEN OTHERS;
	END concurrent;