代码搜索:Comp
找到约 10,000 项符合「Comp」的源代码
代码结果 10,000
www.eeworm.com/read/408853/2241866
vhd sh057.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SH057 IS
PORT(clk2,cp,dir,free: IN STD_LOGIC;
clr:IN STD_LOGIC;
clk3:IN STD_LOGIC;
sw1,sw2,sw3:IN STD_LOGIC;
comp_a,comp_b
www.eeworm.com/read/408853/2241867
vhd sh057.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SH057 IS
PORT(clk2,cp,dir,free: IN STD_LOGIC;
clr:IN STD_LOGIC;
clk3:IN STD_LOGIC;
sw1,sw2,sw3:IN STD_LOGIC;
comp_a,comp_b
www.eeworm.com/read/110205/15539995
bak flash.bak
#include "c:\comp51\reg52.h"
#include "c:\comp51\absacc.h"
#include "intrins.h"
sbit CS=P1^5;
sbit MOSI= P1^3;
sbit MISO= P1^4;
sbit SCK= P1^2;
sbit WP=P1^
www.eeworm.com/read/110205/15540090
h flash.h
#include "c:\comp51\reg52.h"
#include "c:\comp51\absacc.h"
#include "intrins.h"
sbit CS=P1^5;
sbit MOSI= P1^3;
sbit MISO= P1^4;
sbit SCK= P1^2;
sbit WP=P1^
www.eeworm.com/read/418184/10960248
v adc_max186_sm.v
//*****************************************************************************************//
// Project : FPGA based Digital Design using Verilog HDL
// File : adc_max186_sm.v
/
www.eeworm.com/read/292040/8380659
m fftwaveletsynthesis.m
function x=FFTwaveletsynthesis(w,FFTsynthesisfilters,J);
% FFTWAVELETANALYSIS FFT-based implementation of the inverse wavelet
% transform.
% x=FFTwaveletsynthesis(w,FFTsynthesisfilters,J) comp
www.eeworm.com/read/384426/8870125
m compandexpo.m
function varargout = compandexpo(varargin)
% COMPANDEXPO M-file for compandexpo.fig
% COMPANDEXPO, by itself, creates a new COMPANDEXPO or raises the existing
% singleton*.
%
% H = COMP
www.eeworm.com/read/160819/10495419
cpp commtest.cpp
#include
using namespace std;
// this is a sample program for comment removal
int main()
{
int x = 3; // meaningful identifier??
cout
www.eeworm.com/read/466081/7044198
asv comparadct.asv
function varargout = ComparaDCT(varargin)
% COMPARADCT M-file for ComparaDCT.fig
% COMPARADCT, by itself, creates a new COMPARADCT or raises the existing
% singleton*.
%
% H = COMP